TroubleElectrical/FPGA_Uni
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Author SHA1 Message Date
riley 973b9260b6 Fixed (maybe bug) in demo program where program branches back to prior instruction. 2026-10-20 16:21:55 +11:00
riley 5eb78e92e9 Fixed bugs in sign extender 2026-10-20 16:14:02 +11:00
riley b52f01c3be Added some delay to better test final branch/halt. 2026-10-20 16:02:40 +11:00
riley 9648db6e77 Switched to used boolean && rather than bitwise & in sign extender 2026-10-20 16:02:14 +11:00
riley a647305bd9 Fixed bug where ram datawidth was not 2^N. 2026-10-20 16:01:34 +11:00
riley 2f652705cc Fixed timing in testbench for branch iteration. 2026-10-16 12:51:21 +11:00
riley 59f7f372f6 Fixed bug where ASU intermediate was being treated as the overflow flag rather than an intermediate. 2026-10-16 12:33:04 +11:00
riley e7fff9f3dc Added explicit rst input to RAM and PC as well as the MIPS processor. 2026-10-16 12:11:19 +11:00
riley c717bf189c Added comment to document the zero-flag 2026-10-16 11:57:55 +11:00
riley 5ae9125e06 Fixed a couple bugs introduced from merge-conflict resolution 2026-10-16 11:50:07 +11:00
riley 8a682347f0 Merge branch 'main' of ssh://git.rileyk.au:19482/TroubleElectrical/FPGA_Uni 2026-10-16 11:44:03 +11:00
riley 559ff01d69 Fixed printing annoyance. Added variable dumping to a wavefile. Updated delay to 2 units (as there is 1 unit of clk being high and 1 unit low). 
Removed register initialisation code from testbench.
Fixed typo when wanting to check T0 (R8) but was checking R0.
Added explicit if-else begin-end blocks to logging and a simulation exit when the testbench is done.
 2026-10-16 11:41:33 +11:00
riley 92a0cb17da Updated assignment 2 to reflect prior changes. Fixed instruction ordering for register file module (again). Fixed typo that limited the space the ALU could write its flags out to. Swapped ordering to be correct when determining if we are storing the result from ALU or MEM. 
Added a QUARTUS_SYNTH around the display logic at the end of the module.
Partially fixed control_unit module, still seems to need some changes as branching doesn't appear to work at all.
 2026-10-16 11:38:35 +11:00
riley 65be2c2d61 Made sign extension explicit to remove bit indexing (which iverilog doesn't like) and a tad more readable. 2026-10-16 11:35:24 +11:00
riley 878f949e5f Made addrwidth sizing consistent with the 2^N used everywhere 2026-10-16 11:34:31 +11:00
riley 0ea3e0fa12 Added initialisation blocks for PC and GPR's 2026-10-16 11:33:45 +11:00
riley 12ae58ad86 Removed flag assignment from within ALU OP case statement and instead perform it at the end. Made bit index for the ASU OP more explicit. 2026-10-16 11:32:24 +11:00
riley 4c7e2ff085 Fixed instruction width issue in ROM. Stripped all comments to form minimal HEX file to rule out possible parser issues. 2026-10-16 11:29:04 +11:00
riley 8ed06d38e1 Merge branch 'main' of ssh://git.rileyk.au:19482/TroubleElectrical/FPGA_Uni 2026-10-16 03:55:57 +11:00
riley 103aa769fd Added testbench for MIPS processor 2026-10-16 03:54:55 +11:00
riley 19e5843d55 Added testbench for MIPS processor 2026-10-16 03:53:14 +11:00
riley a63d46bc77 Merge branch 'main' of ssh://git.rileyk.au:19482/TroubleElectrical/FPGA_Uni 2026-10-15 15:54:38 +11:00
riley 04d1d3e2fe Added control unit. TODO: Test 2026-10-15 15:53:59 +11:00
riley 5fc24f7859 Temp change to make RAM word-aligned 2026-10-15 15:28:27 +11:00
riley 2e042fbd93 Merge branch 'main' of ssh://git.rileyk.au:19482/TroubleElectrical/FPGA_Uni 2026-10-15 15:18:09 +11:00
riley a336df9d80 Reworked CPU to use control unit 2026-10-15 15:16:57 +11:00
riley 1c93c082ae Merge branch 'main' of ssh://git.rileyk.au:19482/TroubleElectrical/FPGA_Uni 2026-10-15 14:48:06 +11:00
riley d9f44f93df Halfway added imm,branch and mem ops 2026-10-15 14:46:51 +11:00
riley 25ed477df9 Rewrote ternary operator to be less confusing 2026-10-15 14:04:36 +11:00
riley 1e13de9301 Updated assignment2. Created file for testing R-type instructions, still needs to be implemented. Consider using bind to be able to extract inner-scoped variables out for inspection. 2026-10-13 22:26:52 +11:00
riley ac6c4cc094 Added module for sign extension. Needs test cases 2026-10-13 22:24:43 +11:00
riley 75ef513efa Added zero flag to ALU and updated testbench to not fail because of it. TODO: Add cases to test the zero flag 2026-10-13 21:34:25 +11:00
riley f91fe0681a Fixed parameter ordering in instancing 2026-10-13 12:45:15 +11:00
riley a04d6b92cb Updated register file to use 2^n rather than n 2026-10-13 12:43:53 +11:00
riley ba9ab863d8 Fixed ordering for instruction counter and added module output gating for writing 2026-10-13 12:33:24 +11:00
riley 6d731b5a6b Merge branch 'main' of ssh://git.rileyk.au:19482/TroubleElectrical/FPGA_Uni 2026-10-13 12:29:52 +11:00
riley b9623569cf Partially implemented R-type instructions (still need to write rd values) 2026-10-13 12:26:26 +11:00
riley 979f12b692 Added zero initialization for r0 2026-10-12 21:29:07 +11:00
riley 1faa7fc3f0 Updated ram and rom modules so that naming is more consistent 2026-10-12 11:49:35 +11:00
riley 96ecc8553c Merge branch 'main' of https://git.rileyk.au/TroubleElectrical/FPGA_Uni 2026-10-08 15:58:16 +11:00
riley dacc49efac TODO 2026-10-08 15:58:06 +11:00
riley 102d5b4b7a Updated RAM interface to be more inline with ROM interface 2026-10-08 14:56:52 +11:00
riley ab561dd510 Implemented RAM. Possible issue by using async assignments in initial begin. 2026-10-08 14:55:28 +11:00
riley 016fb874e7 Set rom to point to example program 2026-10-08 14:22:00 +11:00
riley 76cd7931b6 Realized that, while the assembled is not binary, it is still loadable by verilog. 2026-10-08 14:18:11 +11:00
riley 0ef2aeeb48 Added instruction counter and register file 2026-10-08 14:13:38 +11:00
riley 5cb48095ce Merge branch 'main' of https://git.rileyk.au/TroubleElectrical/FPGA_Uni 2026-10-08 14:12:56 +11:00
riley aab18425f9 Added test assembly code 2026-10-08 14:08:35 +11:00
riley 3af4bfc875 Added attribution to submission files 2026-09-16 13:35:35 +10:00
riley 900b544bc6 Added python script for invoking icarus verilog. This script has three subcommands; submit, test_submit and test. test is equivalent to the run.bat shell script, submit generates a single-file verilog source suitable for submission. test_submit will run all generated submission testbenches to verify that nothing was broken. 
Renamed submission folder to fix typo.
 2026-09-15 22:00:02 +10:00
riley 6a518dcd42 Merge branch 'main' of ssh://git.rileyk.au:19482/TroubleElectrical/FPGA_Uni 
Merged incomming changes
 2026-09-15 21:29:54 +10:00
riley 392f1f7a27 Updated shifter testbench to work with 2^n widths rather than bitwidths. 2026-09-15 21:29:47 +10:00
riley 287fc1903d Updated default ASU testbench width to be 4-bit to align with seven segment width for demo 2026-09-15 21:28:01 +10:00
riley 19cd7ac177 Updated ALU and ASU modules to conditionally require seven-segment output logic. Used for the assignment 1 demo and MUST be stripped for assignment 2. 2026-09-15 21:27:04 +10:00
riley c4ebde7692 Updated ASU to use an explicit MUX rather than the XOR inversion 'trick' when calculating the operand 2026-09-14 00:13:17 +10:00
riley 4df723318b Ensured case variable assignment is internally consistent with other possibilities to ensure optimal case synthesis 2026-09-13 23:53:47 +10:00
riley 49f539c855 Updated instruction classifier to use combinational logic with a depth of 3 gates (AND, XNOR, HAND) 2026-09-13 23:35:05 +10:00
riley 19ba1bf473 Added header guards to prevent errors from double-inclusions 2026-09-13 23:09:08 +10:00
riley 78efccfe1e Implemented ALU test cases for all operations. Added ALU testbench to active testing. Fixed bug where alu_flags module argument was defined as a 2-element logic array output rather than a 2-bit logic output 2026-09-13 23:08:07 +10:00
riley f69f87ccab Just add cases for ALU testbench. The structure of the ALU testbench is now implemented. 2026-09-10 15:57:56 +10:00
riley cd7074a78c Need to change instruction classifier implementation to use a more parallel architecture as case statements can produce sequential MUX'es 2026-09-10 15:56:59 +10:00
riley 37644c629e Fixed bug of confuddling width with 2^n and w. 2026-09-10 15:42:50 +10:00
riley e9feb3cb8d Merge branch 'main' of ssh://git.rileyk.au:19482/TroubleElectrical/FPGA_Uni 2026-09-10 15:38:50 +10:00
riley 669357ccc0 Implemented ALU. Still needs testbench and testing done. 2026-09-10 15:38:36 +10:00
riley 5acf1c8b87 Fixed bug in adder/subtracter where code assuming width was the bit width was not updated when moving to the 2**N approach required by the assignment. Updated adder/subtracter testbench to correctly instantiate the asser/subtracter and removed unused variable 2026-09-08 22:49:22 +10:00
riley 42f4e661dc Implemented shifter and its test bench code fully 2026-09-08 22:35:14 +10:00
riley 9794f26137 Fixed error in logic unit testbench where it didn't instansiate the DUT at all as well as some faulty test cases and reset logic 2026-09-08 22:00:07 +10:00
riley fabfba7bdd Removed debug statement from instruction classifier testbench 2026-09-08 21:44:36 +10:00
riley f5a2455849 Added testbench for instruction classifier and fixed compilation errors. Should be fine to synthesise but icarus does not like the constant bit extraction in the always_comb block for some reason. 2026-09-08 21:31:18 +10:00
riley 00d9e3de88 Fixed error where assignment was not within a combinational/sequential block 2026-09-08 18:23:27 +10:00
riley b926d71523 Updated seven segment test bench to reflect prior commit 2026-09-03 16:58:11 +10:00
riley 3e8aa911ce Made RSIOut the LSB to correspond with wiring configuration 2026-09-03 16:56:11 +10:00
riley dd5d044da3 Fixed bit ordering in seven segment truth table and test bench 2026-09-03 16:49:46 +10:00
riley a89a66d34d Fixed bug where includes still refered to verilog rather than systemverilog. Inverted test cases in seven segment test bench to reflect changes made to module. There is still a bug with the module where it outputs garbage 2026-09-03 16:32:56 +10:00
riley f881a4126b Inverted seven segment decoder to reflect the common anode 2026-09-03 16:27:01 +10:00
riley 6668969b03 Made it clear that we are using SystemVerilog by renaming HDL files to end in .sv rather than .v 2026-09-03 16:05:52 +10:00
riley 0c21734447 Created general project structure. Only seven segment, logic unit and adder/subtractor modules and tests implemented 2026-09-03 15:25:07 +10:00