Merge branch 'main' of ssh://git.rileyk.au:19482/TroubleElectrical/FPGA_Uni

modules/control_unit.sv

@@ -33,4 +33,4 @@ module control_unit (
     end
 
 endmodule
-`endif
+`endif

modules/ram.sv

@@ -10,7 +10,7 @@ module ram #(addrwidth=9, datawidth=5)(
 );
 
     // TODO: Make this byte-sized, NOT word-sized!
-    logic [2**width-1:0] mem[(2**(addrwidth+$clog2(datawidth)-3))-1:0];
+    logic [2**datawidth-1:0] mem[(2**(addrwidth+$clog2(datawidth)-3))-1:0];
 
     // NOTE: Possible issue with assignments still pending by end of initial block
     initial begin

modules/sign_extender.sv

@@ -8,9 +8,9 @@ module sign_extender #(in_width=4, out_width=5)(
 );
     always_comb begin
         if (op) begin
-            assign ext_val = { {(2**(out_width-in_width)){val[2**in_width-1]}}, val};
+            ext_val = { {(2**(out_width-in_width)){val[2**in_width-1]}}, val};
         end else begin
-            assign ext_val = ({{(2**(out_width-in_width)){1'b0}}, val});
+            ext_val = ({{(2**(out_width-in_width)){1'b0}}, val});
         end
     end
 endmodule