TroubleElectrical/FPGA_Uni
1
0 Fork 0
Code Issues 1 Pull Requests Actions Packages Projects Releases Wiki Activity
43 Commits 2 Branches 0 Tags
900b544bc69664991a9cc19a9d4eb92a20f0c2e9
T
Clone
Open with VS Code Open with VSCodium Open with Intellij IDEA
Download ZIP Download TAR.GZ Download BUNDLE
riley 900b544bc6 Added python script for invoking icarus verilog. This script has three subcommands; submit, test_submit and test. test is equivalent to the run.bat shell script, submit generates a single-file verilog source suitable for submission. test_submit will run all generated submission testbenches to verify that nothing was broken. 
Renamed submission folder to fix typo.
2026-09-15 22:00:02 +10:00
ModelSim
Updated ASU (Q3) to utilise the 7seg for output, confirmed operation of Q1 to Q3 on board
2026-09-15 16:52:48 +10:00
modules
Updated ALU and ASU modules to conditionally require seven-segment output logic. Used for the assignment 1 demo and MUST be stripped for assignment 2.
2026-09-15 21:27:04 +10:00
Quartus
Enabled 2 segments for seven seg display decoder (Q1), most code just needs comments
2026-09-15 21:08:40 +10:00
Submission
Added python script for invoking icarus verilog. This script has three subcommands; submit, test_submit and test. test is equivalent to the run.bat shell script, submit generates a single-file verilog source suitable for submission. test_submit will run all generated submission testbenches to verify that nothing was broken.
2026-09-15 22:00:02 +10:00
tests
Updated shifter testbench to work with 2^n widths rather than bitwidths.
2026-09-15 21:29:47 +10:00
.gitignore
Created general project structure. Only seven segment, logic unit and adder/subtractor modules and tests implemented
2026-09-03 15:25:07 +10:00
isv.py
Added python script for invoking icarus verilog. This script has three subcommands; submit, test_submit and test. test is equivalent to the run.bat shell script, submit generates a single-file verilog source suitable for submission. test_submit will run all generated submission testbenches to verify that nothing was broken.
2026-09-15 22:00:02 +10:00
README.md
Initial commit
2026-09-03 15:04:27 +10:00
run.bat
Fixed bug where includes still refered to verilog rather than systemverilog. Inverted test cases in seven segment test bench to reflect changes made to module. There is still a bug with the module where it outputs garbage
2026-09-03 16:32:56 +10:00

README.md

FPGA_Uni

Reference in new issue View Git Blame Copy Permalink
S
Description
No description provided
Readme
126 MiB
0 Stars 1 Watchers 0 Forks
Languages
SystemVerilog 85.1%
HTML 4.9%
Assembly 4.9%
Scilab 2.5%
Python 2.1%
Other 0.4%