d2ba06b255
Added Hazard Unit file (tested compiling correctly) labelled variables inside off of the Assignment 3 Questions PDF Figure 2. Also have a placeholder MUX to place before the ALU for adding hazard unit functionality
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TroubleElectrical2026-11-08 12:32:40 +11:00
fe53955748
Fixed bug in test code where there was a hazzard, despite testing assuming no hazzard. Updated testbench to reflect this (Ln57-62). Added mem[0x000] to log message when printing registers. Replaced 8 delay with explicit 5x 2 delays. (NOTE: Needed an extra one for ensuring write-back when comparing results. Fixed bug where the wrong registers were being added together when creating the comparison point in the testbench. Fixed testbench bug where S4 was checked twice and S5 not checked at all. Updated display message on test failure to reflect that it is the pipelined version, not the single-cycle.
riley2026-11-05 16:15:06 +11:00
de1f346f64
Updated assignment3 instruction counter code to be more consistent with other modules
riley2026-11-05 15:46:05 +11:00
74a15cf038
Made ROM binary file configurable via a parameter. Updated assignment2 and assignment3 to reflect this. Added bit slicing in assignment2 for ram/rom addresses.
riley2026-11-05 14:27:01 +11:00
38fa35fccd
Fixed initialisation bug and compilation error in gatereg module. Added mips_pipelined to test suite. Fixed several bugs in assignment3 MIPS module
riley2026-11-05 14:10:13 +11:00
f8ea90e41d
Created assignment 3 MIPS module that uses pipelining
riley2026-11-04 17:28:36 +11:00
704286f0e6
Renamed MIPS test to be a single cycle test
riley2026-11-04 15:42:52 +11:00
ef6bd3aec9
Added test assemblies for assignment 3 / pipelining
riley2026-11-04 15:42:22 +11:00
8f9ec010ac
Updated gate register module to support arbitary delays to prevent littering uper-level code with gatereg->gatereg logic values.
riley2026-11-04 15:40:25 +11:00
b046ad7db0
Created register for gating pipeline stage results
riley2026-10-29 15:27:05 +11:00
8b48084fa5
Repaired Sign extender module again to ensure only combinational logic used (There was a compilation error before, also compiled and tested code on board)
TroubleElectrical2026-10-22 15:53:15 +11:00
973b9260b6
Fixed (maybe bug) in demo program where program branches back to prior instruction.
riley2026-10-20 16:21:55 +11:00
5eb78e92e9
Fixed bugs in sign extender
riley2026-10-20 16:14:02 +11:00
b52f01c3be
Added some delay to better test final branch/halt.
riley2026-10-20 16:02:40 +11:00
9648db6e77
Switched to used boolean && rather than bitwise & in sign extender
riley2026-10-20 16:02:14 +11:00
a647305bd9
Fixed bug where ram datawidth was not 2^N.
riley2026-10-20 16:01:34 +11:00
d962a1b557
Added code to display current PC, Removed Blanking from 7seg 4 digits, Changed reset to a switch rather than button Compiled working version for board
TroubleElectrical2026-10-16 14:27:29 +11:00
91a5090528
Added Changes to ModelSim from Modules folder (and small fix for ../hexfile path)
TroubleElectrical2026-10-16 12:59:50 +11:00
2f652705cc
Fixed timing in testbench for branch iteration.
riley2026-10-16 12:51:21 +11:00
59f7f372f6
Fixed bug where ASU intermediate was being treated as the overflow flag rather than an intermediate.
riley2026-10-16 12:33:04 +11:00
e7fff9f3dc
Added explicit rst input to RAM and PC as well as the MIPS processor.
riley2026-10-16 12:11:19 +11:00
c717bf189c
Added comment to document the zero-flag
riley2026-10-16 11:57:55 +11:00
5ae9125e06
Fixed a couple bugs introduced from merge-conflict resolution
riley2026-10-16 11:50:07 +11:00
8a682347f0
Merge branch 'main' of ssh://git.rileyk.au:19482/TroubleElectrical/FPGA_Uni
riley2026-10-16 11:43:43 +11:00
559ff01d69
Fixed printing annoyance. Added variable dumping to a wavefile. Updated delay to 2 units (as there is 1 unit of clk being high and 1 unit low). Removed register initialisation code from testbench. Fixed typo when wanting to check T0 (R8) but was checking R0. Added explicit if-else begin-end blocks to logging and a simulation exit when the testbench is done.
riley2026-10-16 11:41:33 +11:00
92a0cb17da
Updated assignment 2 to reflect prior changes. Fixed instruction ordering for register file module (again). Fixed typo that limited the space the ALU could write its flags out to. Swapped ordering to be correct when determining if we are storing the result from ALU or MEM. Added a QUARTUS_SYNTH around the display logic at the end of the module. Partially fixed control_unit module, still seems to need some changes as branching doesn't appear to work at all.
riley2026-10-16 11:38:35 +11:00
65be2c2d61
Made sign extension explicit to remove bit indexing (which iverilog doesn't like) and a tad more readable.
riley2026-10-16 11:35:24 +11:00
878f949e5f
Made addrwidth sizing consistent with the 2^N used everywhere
riley2026-10-16 11:34:31 +11:00
0ea3e0fa12
Added initialisation blocks for PC and GPR's
riley2026-10-16 11:33:45 +11:00
12ae58ad86
Removed flag assignment from within ALU OP case statement and instead perform it at the end. Made bit index for the ASU OP more explicit.
riley2026-10-16 11:32:24 +11:00
4c7e2ff085
Fixed instruction width issue in ROM. Stripped all comments to form minimal HEX file to rule out possible parser issues.
riley2026-10-16 11:29:04 +11:00
25ed477df9
Rewrote ternary operator to be less confusing
riley2026-10-15 14:04:36 +11:00
1e13de9301
Updated assignment2. Created file for testing R-type instructions, still needs to be implemented. Consider using bind to be able to extract inner-scoped variables out for inspection.
riley2026-10-13 22:26:52 +11:00
ac6c4cc094
Added module for sign extension. Needs test cases
riley2026-10-13 22:24:43 +11:00
75ef513efa
Added zero flag to ALU and updated testbench to not fail because of it. TODO: Add cases to test the zero flag
riley2026-10-13 21:34:25 +11:00
25a953cdc6
Added 4 digit 7seg display module (confirmed working for now), Added Inputs for displaying registers / Program Counter high and low bits, Assigned pins for Display digits, inputs (Labeled HID) and the clk button
TroubleElectrical2026-10-13 16:32:15 +11:00
353923eadf
Updated Assignment to remove ../../ includes (unnesccesary, also SYNTHESIS macro is not used by quartus, so I manually have QUARTUS_SYNTH for those includes)
TroubleElectrical2026-10-13 15:12:00 +11:00
19b07b649d
Repaired last few errors in modules and ensured compilation with QUARTUS_BUILD global flag in Quartus build settings and compiled fully (no errors other than pin assignments)
TroubleElectrical2026-10-13 13:24:44 +11:00
f91fe0681a
Fixed parameter ordering in instancing
riley2026-10-13 12:45:15 +11:00
a04d6b92cb
Updated register file to use 2^n rather than n
riley2026-10-13 12:43:53 +11:00
ba9ab863d8
Fixed ordering for instruction counter and added module output gating for writing
riley2026-10-13 12:33:24 +11:00
6d731b5a6b
Merge branch 'main' of ssh://git.rileyk.au:19482/TroubleElectrical/FPGA_Uni
riley2026-10-13 12:29:52 +11:00
b9623569cf
Partially implemented R-type instructions (still need to write rd values)
riley2026-10-13 12:26:26 +11:00
900b544bc6
Added python script for invoking icarus verilog. This script has three subcommands; submit, test_submit and test. test is equivalent to the run.bat shell script, submit generates a single-file verilog source suitable for submission. test_submit will run all generated submission testbenches to verify that nothing was broken. Renamed submission folder to fix typo.
riley2026-09-15 22:00:02 +10:00
392f1f7a27
Updated shifter testbench to work with 2^n widths rather than bitwidths.
riley2026-09-15 21:29:47 +10:00
287fc1903d
Updated default ASU testbench width to be 4-bit to align with seven segment width for demo
riley2026-09-15 21:28:01 +10:00
19cd7ac177
Updated ALU and ASU modules to conditionally require seven-segment output logic. Used for the assignment 1 demo and MUST be stripped for assignment 2.
riley2026-09-15 21:27:04 +10:00
afa8d9d4db
Enabled 2 segments for seven seg display decoder (Q1), most code just needs comments
TroubleElectrical2026-09-15 21:08:40 +10:00
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riley