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FPGA_Uni
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riley
00d9e3de88
Fixed error where assignment was not within a combinational/sequential block
2026-09-08 18:23:27 +10:00
ModelSim
Added ModelSim folder (and have to add files into it as to allow for different testbench code)
2026-09-08 16:32:01 +10:00
modules
Fixed error where assignment was not within a combinational/sequential block
2026-09-08 18:23:27 +10:00
Quartus
Added ModelSim folder (and have to add files into it as to allow for different testbench code)
2026-09-08 16:32:01 +10:00
tests
Added ModelSim folder (and have to add files into it as to allow for different testbench code)
2026-09-08 16:32:01 +10:00
.gitignore
Created general project structure. Only seven segment, logic unit and adder/subtractor modules and tests implemented
2026-09-03 15:25:07 +10:00
README.md
Initial commit
2026-09-03 15:04:27 +10:00
run.bat
Fixed bug where includes still refered to verilog rather than systemverilog. Inverted test cases in seven segment test bench to reflect changes made to module. There is still a bug with the module where it outputs garbage
2026-09-03 16:32:56 +10:00
README.md
FPGA_Uni
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