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FPGA_Uni
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riley
cd7074a78c
Need to change instruction classifier implementation to use a more parallel architecture as case statements can produce sequential MUX'es
2026-09-10 15:56:59 +10:00
ModelSim
Added ASU (Q3) testbench to the modelsim projects folder (also confirmed operation of q2)
2026-09-10 15:24:44 +10:00
modules
Need to change instruction classifier implementation to use a more parallel architecture as case statements can produce sequential MUX'es
2026-09-10 15:56:59 +10:00
Quartus
Added ASU (Q3) testbench to the modelsim projects folder (also confirmed operation of q2)
2026-09-10 15:24:44 +10:00
tests
Fixed bug in adder/subtracter where code assuming width was the bit width was not updated when moving to the 2**N approach required by the assignment. Updated adder/subtracter testbench to correctly instantiate the asser/subtracter and removed unused variable
2026-09-08 22:49:22 +10:00
.gitignore
Created general project structure. Only seven segment, logic unit and adder/subtractor modules and tests implemented
2026-09-03 15:25:07 +10:00
README.md
Initial commit
2026-09-03 15:04:27 +10:00
run.bat
Fixed bug where includes still refered to verilog rather than systemverilog. Inverted test cases in seven segment test bench to reflect changes made to module. There is still a bug with the module where it outputs garbage
2026-09-03 16:32:56 +10:00
README.md
FPGA_Uni
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