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TroubleElectrical/FPGA_Uni
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f881a4126b9f0774a5e7413814dec82b6ec4fc4b
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riley f881a4126b Inverted seven segment decoder to reflect the common anode
2026-09-03 16:27:01 +10:00
modules
Inverted seven segment decoder to reflect the common anode
2026-09-03 16:27:01 +10:00
tests
Made it clear that we are using SystemVerilog by renaming HDL files to end in .sv rather than .v
2026-09-03 16:05:52 +10:00
.gitignore
Created general project structure. Only seven segment, logic unit and adder/subtractor modules and tests implemented
2026-09-03 15:25:07 +10:00
README.md
Initial commit
2026-09-03 15:04:27 +10:00
run.bat
Created general project structure. Only seven segment, logic unit and adder/subtractor modules and tests implemented
2026-09-03 15:25:07 +10:00

README.md

FPGA_Uni

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