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FPGA_Uni
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riley
979f12b692
Added zero initialization for r0
2026-10-12 21:29:07 +11:00
asm
Realized that, while the assembled is not binary, it is still loadable by verilog.
2026-10-08 14:18:11 +11:00
ModelSim
Updated ModelSim Files
2026-09-16 10:15:08 +10:00
modules
Added zero initialization for r0
2026-10-12 21:29:07 +11:00
Quartus
Updated register_file.sv with proper naming scheme and 32bit width
2026-10-08 15:10:40 +11:00
Submission
Added attribution to submission files
2026-09-16 13:35:35 +10:00
tests
Added comments to Logic Unit (Q2) and added to submission file
2026-09-16 12:38:06 +10:00
.gitignore
Created general project structure. Only seven segment, logic unit and adder/subtractor modules and tests implemented
2026-09-03 15:25:07 +10:00
isv.py
Added python script for invoking icarus verilog. This script has three subcommands; submit, test_submit and test. test is equivalent to the run.bat shell script, submit generates a single-file verilog source suitable for submission. test_submit will run all generated submission testbenches to verify that nothing was broken.
2026-09-15 22:00:02 +10:00
README.md
Initial commit
2026-09-03 15:04:27 +10:00
run.bat
Fixed bug where includes still refered to verilog rather than systemverilog. Inverted test cases in seven segment test bench to reflect changes made to module. There is still a bug with the module where it outputs garbage
2026-09-03 16:32:56 +10:00
README.md
FPGA_Uni
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