TroubleElectrical/FPGA_Uni
1
0 Fork 0
Code Issues 1 Pull Requests Actions Packages Projects Releases Wiki Activity
114 Commits 2 Branches 0 Tags
59f7f372f6afd614f745e7d9f141c84d04e933d3
T
Clone
Open with VS Code Open with VSCodium Open with Intellij IDEA
Download ZIP Download TAR.GZ Download BUNDLE
riley 59f7f372f6 Fixed bug where ASU intermediate was being treated as the overflow flag rather than an intermediate.
2026-10-16 12:33:04 +11:00
asm
Fixed instruction width issue in ROM. Stripped all comments to form minimal HEX file to rule out possible parser issues.
2026-10-16 11:29:04 +11:00
ModelSim
Updated RAM code to make sure Bus width is 32 bits
2026-10-16 11:32:47 +11:00
modules
Fixed bug where ASU intermediate was being treated as the overflow flag rather than an intermediate.
2026-10-16 12:33:04 +11:00
Quartus
Updated RAM code to make sure Bus width is 32 bits
2026-10-16 11:32:47 +11:00
Submission
Added attribution to submission files
2026-09-16 13:35:35 +10:00
tests
Added explicit rst input to RAM and PC as well as the MIPS processor.
2026-10-16 12:11:19 +11:00
.gitignore
Created general project structure. Only seven segment, logic unit and adder/subtractor modules and tests implemented
2026-09-03 15:25:07 +10:00
isv.py
Added python script for invoking icarus verilog. This script has three subcommands; submit, test_submit and test. test is equivalent to the run.bat shell script, submit generates a single-file verilog source suitable for submission. test_submit will run all generated submission testbenches to verify that nothing was broken.
2026-09-15 22:00:02 +10:00
README.md
Initial commit
2026-09-03 15:04:27 +10:00
run.bat
Fixed bug where includes still refered to verilog rather than systemverilog. Inverted test cases in seven segment test bench to reflect changes made to module. There is still a bug with the module where it outputs garbage
2026-09-03 16:32:56 +10:00

README.md

FPGA_Uni

Reference in new issue View Git Blame Copy Permalink
S
Description
No description provided
Readme
126 MiB
0 Stars 1 Watchers 0 Forks
Languages
SystemVerilog 85.1%
HTML 4.9%
Assembly 4.9%
Scilab 2.5%
Python 2.1%
Other 0.4%