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FPGA_Uni
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riley
78efccfe1e
Implemented ALU test cases for all operations. Added ALU testbench to active testing. Fixed bug where alu_flags module argument was defined as a 2-element logic array output rather than a 2-bit logic output
2026-09-13 23:08:07 +10:00
ModelSim
Added ASU (Q3) testbench to the modelsim projects folder (also confirmed operation of q2)
2026-09-10 15:24:44 +10:00
modules
Implemented ALU test cases for all operations. Added ALU testbench to active testing. Fixed bug where alu_flags module argument was defined as a 2-element logic array output rather than a 2-bit logic output
2026-09-13 23:08:07 +10:00
Quartus
Added ASU (Q3) testbench to the modelsim projects folder (also confirmed operation of q2)
2026-09-10 15:24:44 +10:00
tests
Implemented ALU test cases for all operations. Added ALU testbench to active testing. Fixed bug where alu_flags module argument was defined as a 2-element logic array output rather than a 2-bit logic output
2026-09-13 23:08:07 +10:00
.gitignore
Created general project structure. Only seven segment, logic unit and adder/subtractor modules and tests implemented
2026-09-03 15:25:07 +10:00
README.md
Initial commit
2026-09-03 15:04:27 +10:00
run.bat
Fixed bug where includes still refered to verilog rather than systemverilog. Inverted test cases in seven segment test bench to reflect changes made to module. There is still a bug with the module where it outputs garbage
2026-09-03 16:32:56 +10:00
README.md
FPGA_Uni
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