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FPGA_Uni
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riley
b926d71523
Updated seven segment test bench to reflect prior commit
2026-09-03 16:58:11 +10:00
modules
Made RSIOut the LSB to correspond with wiring configuration
2026-09-03 16:56:11 +10:00
Quartus
/A1_Q1
Including quartus prime lite edition project folders for flashing the project to the board
2026-09-03 16:34:31 +10:00
tests
Updated seven segment test bench to reflect prior commit
2026-09-03 16:58:11 +10:00
.gitignore
Created general project structure. Only seven segment, logic unit and adder/subtractor modules and tests implemented
2026-09-03 15:25:07 +10:00
README.md
Initial commit
2026-09-03 15:04:27 +10:00
run.bat
Fixed bug where includes still refered to verilog rather than systemverilog. Inverted test cases in seven segment test bench to reflect changes made to module. There is still a bug with the module where it outputs garbage
2026-09-03 16:32:56 +10:00
README.md
FPGA_Uni
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