TroubleElectrical/FPGA_Uni
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8b48084fa558380f1f468c2148708cb2ab49f94d
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84 Commits
Author SHA1 Message Date
riley 102d5b4b7a Updated RAM interface to be more inline with ROM interface 2026-10-08 14:56:52 +11:00
riley ab561dd510 Implemented RAM. Possible issue by using async assignments in initial begin. 2026-10-08 14:55:28 +11:00
riley 016fb874e7 Set rom to point to example program 2026-10-08 14:22:00 +11:00
riley 0ef2aeeb48 Added instruction counter and register file 2026-10-08 14:13:38 +11:00
TroubleElectrical 9e3525fcac Added Byte addressable ROM from Slides 2026-10-06 16:28:23 +11:00
TroubleElectrical 3145dd6a21 Added ROM file from MIPS Architecture Slide Part 1 2026-10-06 16:03:03 +11:00
TroubleElectrical 179eb469c4 Removed seven segment code from alu and asu 2026-09-24 15:37:48 +10:00
TroubleElectrical ae8ac98e8d Added Q5 comments and sumbission 2026-09-16 12:54:18 +10:00
TroubleElectrical 13f34e62c6 Added Q4 sumbission and comments 2026-09-16 12:50:58 +10:00
TroubleElectrical 56ade6b426 Added comments to Logic Unit (Q2) and added to submission file 2026-09-16 12:38:06 +10:00
riley 19cd7ac177 Updated ALU and ASU modules to conditionally require seven-segment output logic. Used for the assignment 1 demo and MUST be stripped for assignment 2. 2026-09-15 21:27:04 +10:00
TroubleElectrical 9583abd307 Updated shifter (Q5) to use proper 2**width approach and corrected the logic such that C is width bits wide, and b is 2**width (as defined in Q5 B) 2026-09-15 19:43:28 +10:00
TroubleElectrical 9d0c7011ce Updated ALU (Q4) with 7seg and confirmed operation on board 2026-09-15 19:05:04 +10:00
TroubleElectrical 9e5fb6f52b Updated ASU (Q3) to utilise the 7seg for output, confirmed operation of Q1 to Q3 on board 2026-09-15 16:52:48 +10:00
riley c4ebde7692 Updated ASU to use an explicit MUX rather than the XOR inversion 'trick' when calculating the operand 2026-09-14 00:13:17 +10:00
riley 4df723318b Ensured case variable assignment is internally consistent with other possibilities to ensure optimal case synthesis 2026-09-13 23:53:47 +10:00
riley 49f539c855 Updated instruction classifier to use combinational logic with a depth of 3 gates (AND, XNOR, HAND) 2026-09-13 23:35:05 +10:00
riley 19ba1bf473 Added header guards to prevent errors from double-inclusions 2026-09-13 23:09:08 +10:00
riley 78efccfe1e Implemented ALU test cases for all operations. Added ALU testbench to active testing. Fixed bug where alu_flags module argument was defined as a 2-element logic array output rather than a 2-bit logic output 2026-09-13 23:08:07 +10:00
riley cd7074a78c Need to change instruction classifier implementation to use a more parallel architecture as case statements can produce sequential MUX'es 2026-09-10 15:56:59 +10:00
riley 37644c629e Fixed bug of confuddling width with 2^n and w. 2026-09-10 15:42:50 +10:00
riley 669357ccc0 Implemented ALU. Still needs testbench and testing done. 2026-09-10 15:38:36 +10:00
TroubleElectrical dc32347c9b Updated ALU code with updated 2**width approach and assigned temporary pins to ASU (Q3) 2026-09-09 14:27:11 +10:00
riley 5acf1c8b87 Fixed bug in adder/subtracter where code assuming width was the bit width was not updated when moving to the 2**N approach required by the assignment. Updated adder/subtracter testbench to correctly instantiate the asser/subtracter and removed unused variable 2026-09-08 22:49:22 +10:00
riley 42f4e661dc Implemented shifter and its test bench code fully 2026-09-08 22:35:14 +10:00
riley f5a2455849 Added testbench for instruction classifier and fixed compilation errors. Should be fine to synthesise but icarus does not like the constant bit extraction in the always_comb block for some reason. 2026-09-08 21:31:18 +10:00
riley 00d9e3de88 Fixed error where assignment was not within a combinational/sequential block 2026-09-08 18:23:27 +10:00
TroubleElectrical 60e5dae43b Added ModelSim folder (and have to add files into it as to allow for different testbench code) 2026-09-08 16:32:01 +10:00
TroubleElectrical 2208eb4f16 Updated Q2 project and LU code such that it operates properly on the board. Changed to utilising a case statement for easier readability and also compiled and tested the code on the board. 2026-09-08 15:36:51 +10:00
riley 3e8aa911ce Made RSIOut the LSB to correspond with wiring configuration 2026-09-03 16:56:11 +10:00
riley dd5d044da3 Fixed bit ordering in seven segment truth table and test bench 2026-09-03 16:49:46 +10:00
riley f881a4126b Inverted seven segment decoder to reflect the common anode 2026-09-03 16:27:01 +10:00
riley 6668969b03 Made it clear that we are using SystemVerilog by renaming HDL files to end in .sv rather than .v 2026-09-03 16:05:52 +10:00
riley 0c21734447 Created general project structure. Only seven segment, logic unit and adder/subtractor modules and tests implemented 2026-09-03 15:25:07 +10:00