Added Q4 sumbission and comments

modules/alu.sv

@@ -15,7 +15,7 @@ module alu #(parameter width=2)(input logic [3:0] op,
 `else
     );
 `endif
-
+    // intermediate logic for handling asu output
     logic [0:0] asu_op;
     logic [2**width-1:0] asu_out;
     logic [1:0] asu_flags;
@@ -54,4 +54,4 @@ module alu #(parameter width=2)(input logic [3:0] op,
 	    seven_seg dut(OUT_1, 1'b1, out_seg1);
     `endif
 endmodule
-`endif
+`endif