riley dd5d044da3 Fixed bit ordering in seven segment truth table and test bench

2026-09-03 16:49:46 +10:00

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alu.sv

Made it clear that we are using SystemVerilog by renaming HDL files to end in .sv rather than .v

2026-09-03 16:05:52 +10:00

asu.sv

Made it clear that we are using SystemVerilog by renaming HDL files to end in .sv rather than .v

2026-09-03 16:05:52 +10:00

instruction_classifier.sv

Made it clear that we are using SystemVerilog by renaming HDL files to end in .sv rather than .v

2026-09-03 16:05:52 +10:00

lu.sv

Made it clear that we are using SystemVerilog by renaming HDL files to end in .sv rather than .v

2026-09-03 16:05:52 +10:00

seven_seg.sv

Fixed bit ordering in seven segment truth table and test bench

2026-09-03 16:49:46 +10:00

shifter.sv

Made it clear that we are using SystemVerilog by renaming HDL files to end in .sv rather than .v

2026-09-03 16:05:52 +10:00