Created general project structure. Only seven segment, logic unit and adder/subtractor modules and tests implemented

modules/alu.v

@@ -0,0 +1,20 @@
+`include "asu.v"
+`include "lu.v"
+
+// flags[0:0] = Cout
+// flags[1:1] = Overflow
+module alu #(width=8)(input logic [3:0] op,
+    input logic [width-1:0] A, input logic [width-1:0] B.
+    output logic [width-1:0] OUT_1, output logic flags[1:0]);
+
+    logic [width-1:0] asu_out;
+    logic [1:0] asu_flags;
+    logic [0:0] asu_op;
+    asu #(width) adder_unit(asu_op, A, B, asu_out, asu_flags[0], asu_flags[1]);
+
+    logic [width-1:0] lu_out;
+    lu #(width) logic_unit(op[1:0], A, B, lu_out);
+
+    // Cout = asu_flags[0]
+    // Overflow = asu_flags[0] ^ asu_flags[1]
+endmodule

modules/asu.v

@@ -0,0 +1,16 @@
+module asu #(width=8)(input logic [0:0] op,
+    input logic[width-1:0] A, input logic[width-1:0] B,
+    output logic[width-1:0] OUT_1, output logic[0:0] COUT, output logic[0:0] OUT_CIN);
+
+    logic [width-1:0] operand;
+    always_comb begin
+        // A + (sub) ? B : -B
+        // Adds an extra bit to all operands to calculate the carry bit. Not optimal for hardware synthesis
+        operand = (B ^ {(width){op}});
+        {COUT, OUT_1} = A + operand + {{(width-1){1'b0}}, op};
+    end
+
+    // Need to do this outside of the always_comb block because parameter-based bitslicing/indexing isn't supported?
+    // Cin for width-2'th bit to later be xor'ed with COUT to determine if a signed overflow occured for the MIPS architecture
+    assign OUT_CIN = A[width-1] ^ operand[width-1] ^ OUT_1[width-1];
+endmodule

modules/instruction_classifier.v

@@ -0,0 +1,25 @@
+module instruction_classifier(input logic op[5:0],
+    output logic[0:0] R, output logic[0:0] B1, output logic[0:0] J,
+    output logic[0:0] B2, output logic[0:0] I, output logic[0:0] F,
+    output logic[0:0] M);
+
+    logic [6:0] OUT_1;
+    casez (op)
+        6'b1?????: OUT_1 = 7'b1000000;
+        6'b01????: OUT_1 = 7'b0100000;
+        6'b001???: OUT_1 = 7'b0010000;
+        6'b0001??: OUT_1 = 7'b0001000;
+        6'b00001?: OUT_1 = 7'b0000100;
+        6'b000001: OUT_1 = 7'b0000010;
+        6'b000000: OUT_1 = 7'b0000001;
+    endcase
+
+    assign R  = OUT_1[6];
+    assign B1 = OUT_1[5];
+    assign J  = OUT_1[4];
+    assign B2 = OUT_1[3];
+    assign I  = OUT_1[2];
+    assign F  = OUT_1[1];
+    assign M  = OUT_1[0];
+
+endmodule

modules/lu.v

@@ -0,0 +1,12 @@
+module lu #(width=8) (
+    input logic [1:0] op,
+    input logic [width-1:0] A, input logic [width-1:0] B,
+    output logic [width-1:0] OUT_1);
+
+    always_comb begin
+        if      (op == 2'b00) OUT_1 =   A & B;
+        else if (op == 2'b01) OUT_1 =   A | B;
+        else if (op == 2'b10) OUT_1 =   A ^ B;
+        else if (op == 2'b10) OUT_1 = ~(A | B);
+    end
+endmodule

modules/seven_seg.v

@@ -0,0 +1,23 @@
+module seven_seg(input logic [3:0] num, input logic [0:0] rbi_inv, output logic [7:0] segments);
+        always_comb begin
+           case (num)
+               4'b0000: segments = (rbi_inv) ? 8'b11111101 : 8'b00000000;
+               4'b0001: segments = 8'b01100001;
+               4'b0010: segments = 8'b11011011;
+               4'b0011: segments = 8'b11110011;
+               4'b0100: segments = 8'b01100111;
+               4'b0101: segments = 8'b10110111;
+               4'b0110: segments = 8'b10111111;
+               4'b0111: segments = 8'b11100001;
+               4'b1000: segments = 8'b11111111;
+               4'b1001: segments = 8'b11100111;
+               4'b1010: segments = 8'b11101111;
+               4'b1011: segments = 8'b00111111;
+               4'b1100: segments = 8'b10011101;
+               4'b1101: segments = 8'b01111011;
+               4'b1110: segments = 8'b10011111;
+               4'b1111: segments = 8'b10001111;
+               default: segments = 8'bxxxxxxxx;
+           endcase     
+        end
+endmodule

modules/shifter.v

@@ -0,0 +1,13 @@
+module shifter #(width=8)(input logic op[1:0],
+    input logic[width-1:0] A, input logic[width-1:0] B,
+    output logic[width-1:0] OUT_1);
+
+    always_comb begin
+        case (op)
+            00: OUT_1 = A << B;
+            01: OUT_1 = A >> B;
+            10: OUT_1 = $signed(A) >>> B;
+            default:;
+        endcase
+    end    
+endmodule