riley 49f539c855 Updated instruction classifier to use combinational logic with a depth of 3 gates (AND, XNOR, HAND)

2026-09-13 23:35:05 +10:00

..

alu.sv

Implemented ALU test cases for all operations. Added ALU testbench to active testing. Fixed bug where alu_flags module argument was defined as a 2-element logic array output rather than a 2-bit logic output

2026-09-13 23:08:07 +10:00

alu.sv.bak

Updated ALU code with updated 2**width approach and assigned temporary pins to ASU (Q3)

2026-09-09 14:27:11 +10:00

asu.sv

Added header guards to prevent errors from double-inclusions

2026-09-13 23:09:08 +10:00

asu.sv.bak

Added ModelSim folder (and have to add files into it as to allow for different testbench code)

2026-09-08 16:32:01 +10:00

instruction_classifier.sv

Updated instruction classifier to use combinational logic with a depth of 3 gates (AND, XNOR, HAND)

2026-09-13 23:35:05 +10:00

lu.sv

Added header guards to prevent errors from double-inclusions

2026-09-13 23:09:08 +10:00

lu.sv.bak

Updated Q2 project and LU code such that it operates properly on the board. Changed to utilising a case statement for easier readability and also compiled and tested the code on the board.

2026-09-08 15:36:51 +10:00

seven_seg.sv

Added header guards to prevent errors from double-inclusions

2026-09-13 23:09:08 +10:00

shifter.sv

Added header guards to prevent errors from double-inclusions

2026-09-13 23:09:08 +10:00