riley 78efccfe1e Implemented ALU test cases for all operations. Added ALU testbench to active testing. Fixed bug where alu_flags module argument was defined as a 2-element logic array output rather than a 2-bit logic output

2026-09-13 23:08:07 +10:00

..

alu.sv

Implemented ALU test cases for all operations. Added ALU testbench to active testing. Fixed bug where alu_flags module argument was defined as a 2-element logic array output rather than a 2-bit logic output

2026-09-13 23:08:07 +10:00

alu.sv.bak

Updated ALU code with updated 2**width approach and assigned temporary pins to ASU (Q3)

2026-09-09 14:27:11 +10:00

asu.sv

Fixed bug in adder/subtracter where code assuming width was the bit width was not updated when moving to the 2**N approach required by the assignment. Updated adder/subtracter testbench to correctly instantiate the asser/subtracter and removed unused variable

2026-09-08 22:49:22 +10:00

asu.sv.bak

Added ModelSim folder (and have to add files into it as to allow for different testbench code)

2026-09-08 16:32:01 +10:00

instruction_classifier.sv

Need to change instruction classifier implementation to use a more parallel architecture as case statements can produce sequential MUX'es

2026-09-10 15:56:59 +10:00

lu.sv

Updated Q2 project and LU code such that it operates properly on the board. Changed to utilising a case statement for easier readability and also compiled and tested the code on the board.

2026-09-08 15:36:51 +10:00

lu.sv.bak

Updated Q2 project and LU code such that it operates properly on the board. Changed to utilising a case statement for easier readability and also compiled and tested the code on the board.

2026-09-08 15:36:51 +10:00

seven_seg.sv

Made RSIOut the LSB to correspond with wiring configuration

2026-09-03 16:56:11 +10:00

shifter.sv

Implemented shifter and its test bench code fully

2026-09-08 22:35:14 +10:00