Updated ASU (Q3) to utilise the 7seg for output, confirmed operation of Q1 to Q3 on board

modules/asu.sv

@@ -1,11 +1,13 @@
 `ifndef ASU_H_SV
 `define ASU_H_SV
 
+`include "seven_seg.sv"
 module asu #(parameter width = 2)(
 	input logic [0:0] op,
 	input logic[2**width-1:0] A, input logic[2**width-1:0] B,
-   output logic[2**width-1:0] OUT_1, output logic[0:0] COUT, output logic[0:0] OUT_CIN);
-
+   output logic[2**width-1:0] OUT_1, output logic[0:0] COUT, output logic[0:0] OUT_CIN,
+	output logic[7:0] out_seg_1);
+	
     logic [2**width-1:0] operand;
     always_comb begin
         // A + (sub) ? B : -B
@@ -18,5 +20,7 @@ module asu #(parameter width = 2)(
     // Need to do this outside of the always_comb block because parameter-based bitslicing/indexing isn't supported?
     // Cin for final bit in adder to later be xor'ed with COUT to determine if a signed overflow occured for the MIPS architecture
     assign OUT_CIN = A[2**width-1] ^ operand[2**width-1] ^ OUT_1[2**width-1];
+	 
+	 seven_seg dut(OUT_1, 1, out_seg_1);
 endmodule
 `endif