TroubleElectrical 60e5dae43b Added ModelSim folder (and have to add files into it as to allow for different testbench code)

2026-09-08 16:32:01 +10:00

..

alu.sv

Made it clear that we are using SystemVerilog by renaming HDL files to end in .sv rather than .v

2026-09-03 16:05:52 +10:00

asu.sv

Added ModelSim folder (and have to add files into it as to allow for different testbench code)

2026-09-08 16:32:01 +10:00

asu.sv.bak

Added ModelSim folder (and have to add files into it as to allow for different testbench code)

2026-09-08 16:32:01 +10:00

instruction_classifier.sv

Made it clear that we are using SystemVerilog by renaming HDL files to end in .sv rather than .v

2026-09-03 16:05:52 +10:00

lu.sv

Updated Q2 project and LU code such that it operates properly on the board. Changed to utilising a case statement for easier readability and also compiled and tested the code on the board.

2026-09-08 15:36:51 +10:00

lu.sv.bak

Updated Q2 project and LU code such that it operates properly on the board. Changed to utilising a case statement for easier readability and also compiled and tested the code on the board.

2026-09-08 15:36:51 +10:00

seven_seg.sv

Made RSIOut the LSB to correspond with wiring configuration

2026-09-03 16:56:11 +10:00

shifter.sv

Made it clear that we are using SystemVerilog by renaming HDL files to end in .sv rather than .v

2026-09-03 16:05:52 +10:00