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Updated instruction classifier to use combinational logic with a depth of 3 gates (AND, XNOR, HAND)

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riley committed 2026-09-13 23:35:05 +10:00
1 parent 19ba1bf473
commit 49f539c855
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modules/instruction_classifier.sv
+10 -20
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@@ -1,31 +1,21 @@
`ifndef INSTRUCTION_CLASSIFIER_H_SV
`define INSTRUCTION_CLASSIFIER_H_SV
// TODO: This needs to be reworked to use manual mux-ing as to ensure low gate delay
module instruction_classifier(input logic[5:0] op,
output logic[0:0] R, output logic[0:0] B1, output logic[0:0] J,
output logic[0:0] B2, output logic[0:0] I, output logic[0:0] F,
output logic[0:0] M);
always_comb begin
logic [6:0] OUT_1;
casez (op)
6'b1?????: OUT_1 = 7'b1000000;
6'b01????: OUT_1 = 7'b0100000;
6'b001???: OUT_1 = 7'b0010000;
6'b0001??: OUT_1 = 7'b0001000;
6'b00001?: OUT_1 = 7'b0000100;
6'b000001: OUT_1 = 7'b0000010;
6'b000000: OUT_1 = 7'b0000001;
default: OUT_1 = 7'bxxxxxxx;
endcase
R = OUT_1[6];
B1 = OUT_1[5];
J = OUT_1[4];
B2 = OUT_1[3];
I = OUT_1[2];
F = OUT_1[1];
M = OUT_1[0];
// Performs a rolling equals check
// Uses an AND mask to mask off bits we don't care about
// And a equals operator to perform a bitwise XNOR followed by a horizontal AND
R = ( (op & 6'b111111) == 6'b000000);
B1= ( (op & 6'b111111) == 6'b000001);
J = ( (op & 6'b111110) == 6'b000010);
B2= ( (op & 6'b111100) == 6'b000100);
I = ( (op & 6'b111000) == 6'b001000);
F = ( (op & 6'b110000) == 6'b010000);
M = ( (op & 6'b100000) == 6'b100000);
end
endmodule
`endif