TroubleElectrical/FPGA_Uni
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Author SHA1 Message Date
riley ac6c4cc094 Added module for sign extension. Needs test cases 2026-10-13 22:24:43 +11:00
riley 75ef513efa Added zero flag to ALU and updated testbench to not fail because of it. TODO: Add cases to test the zero flag 2026-10-13 21:34:25 +11:00
TroubleElectrical 80416e1f8a TODO: Remove Shifter Code 2026-10-13 16:57:03 +11:00
TroubleElectrical 25a953cdc6 Added 4 digit 7seg display module (confirmed working for now), 
Added Inputs for displaying registers / Program Counter high and low bits,
Assigned pins for Display digits, inputs (Labeled HID) and the clk button
 2026-10-13 16:32:15 +11:00
TroubleElectrical 353923eadf Updated Assignment to remove ../../ includes (unnesccesary, also SYNTHESIS macro is not used by quartus, so I manually have QUARTUS_SYNTH for those includes) 2026-10-13 15:12:00 +11:00
TroubleElectrical 19b07b649d Repaired last few errors in modules and ensured compilation with QUARTUS_BUILD global flag in Quartus build settings and compiled fully (no errors other than pin assignments) 2026-10-13 13:24:44 +11:00
riley f91fe0681a Fixed parameter ordering in instancing 2026-10-13 12:45:15 +11:00
riley a04d6b92cb Updated register file to use 2^n rather than n 2026-10-13 12:43:53 +11:00
riley ba9ab863d8 Fixed ordering for instruction counter and added module output gating for writing 2026-10-13 12:33:24 +11:00
riley 6d731b5a6b Merge branch 'main' of ssh://git.rileyk.au:19482/TroubleElectrical/FPGA_Uni 2026-10-13 12:29:52 +11:00
riley b9623569cf Partially implemented R-type instructions (still need to write rd values) 2026-10-13 12:26:26 +11:00
TroubleElectrical e57e8f362a Updated assignment 2 dependency modules (currently 8 errors in compile) 2026-10-13 12:23:52 +11:00
TroubleElectrical 8675f5b8ee Made Assignment 2 Quartus Project 2026-10-13 12:04:49 +11:00
riley 979f12b692 Added zero initialization for r0 2026-10-12 21:29:07 +11:00
riley 1faa7fc3f0 Updated ram and rom modules so that naming is more consistent 2026-10-12 11:49:35 +11:00
riley 96ecc8553c Merge branch 'main' of https://git.rileyk.au/TroubleElectrical/FPGA_Uni 2026-10-08 15:58:16 +11:00
riley dacc49efac TODO 2026-10-08 15:58:06 +11:00
TroubleElectrical b49e294b7d Updated register_file.sv with proper naming scheme and 32bit width 2026-10-08 15:10:40 +11:00
riley 102d5b4b7a Updated RAM interface to be more inline with ROM interface 2026-10-08 14:56:52 +11:00
riley ab561dd510 Implemented RAM. Possible issue by using async assignments in initial begin. 2026-10-08 14:55:28 +11:00
riley 016fb874e7 Set rom to point to example program 2026-10-08 14:22:00 +11:00
riley 76cd7931b6 Realized that, while the assembled is not binary, it is still loadable by verilog. 2026-10-08 14:18:11 +11:00
riley 0ef2aeeb48 Added instruction counter and register file 2026-10-08 14:13:38 +11:00
riley 5cb48095ce Merge branch 'main' of https://git.rileyk.au/TroubleElectrical/FPGA_Uni 2026-10-08 14:12:56 +11:00
riley aab18425f9 Added test assembly code 2026-10-08 14:08:35 +11:00
TroubleElectrical 9e3525fcac Added Byte addressable ROM from Slides 2026-10-06 16:28:23 +11:00
TroubleElectrical 3145dd6a21 Added ROM file from MIPS Architecture Slide Part 1 2026-10-06 16:03:03 +11:00
TroubleElectrical 179eb469c4 Removed seven segment code from alu and asu 2026-09-24 15:37:48 +10:00
riley 3af4bfc875 Added attribution to submission files 2026-09-16 13:35:35 +10:00
TroubleElectrical 64cd876f12 Added attribution for submission files 2026-09-16 13:01:43 +10:00
TroubleElectrical cbb5bb917a Added Q6 submission 2026-09-16 12:56:48 +10:00
TroubleElectrical ae8ac98e8d Added Q5 comments and sumbission 2026-09-16 12:54:18 +10:00
TroubleElectrical 13f34e62c6 Added Q4 sumbission and comments 2026-09-16 12:50:58 +10:00
TroubleElectrical 7d489ab77c Added Q3 sumbission and integrated all includes 2026-09-16 12:42:28 +10:00
TroubleElectrical 56ade6b426 Added comments to Logic Unit (Q2) and added to submission file 2026-09-16 12:38:06 +10:00
TroubleElectrical 0947f26727 Added comments to Q1 code and made submission file 2026-09-16 10:33:08 +10:00
TroubleElectrical 00167dabc8 Updated ModelSim Files 2026-09-16 10:15:08 +10:00
riley 900b544bc6 Added python script for invoking icarus verilog. This script has three subcommands; submit, test_submit and test. test is equivalent to the run.bat shell script, submit generates a single-file verilog source suitable for submission. test_submit will run all generated submission testbenches to verify that nothing was broken. 
Renamed submission folder to fix typo.
 2026-09-15 22:00:02 +10:00
riley 6a518dcd42 Merge branch 'main' of ssh://git.rileyk.au:19482/TroubleElectrical/FPGA_Uni 
Merged incomming changes
 2026-09-15 21:29:54 +10:00
riley 392f1f7a27 Updated shifter testbench to work with 2^n widths rather than bitwidths. 2026-09-15 21:29:47 +10:00
riley 287fc1903d Updated default ASU testbench width to be 4-bit to align with seven segment width for demo 2026-09-15 21:28:01 +10:00
riley 19cd7ac177 Updated ALU and ASU modules to conditionally require seven-segment output logic. Used for the assignment 1 demo and MUST be stripped for assignment 2. 2026-09-15 21:27:04 +10:00
TroubleElectrical afa8d9d4db Enabled 2 segments for seven seg display decoder (Q1), most code just needs comments 2026-09-15 21:08:40 +10:00
TroubleElectrical c27a04ef73 Implemented instruction classifier on board (Q6) and added blank submission files (for now) 2026-09-15 20:00:35 +10:00
TroubleElectrical 9583abd307 Updated shifter (Q5) to use proper 2**width approach and corrected the logic such that C is width bits wide, and b is 2**width (as defined in Q5 B) 2026-09-15 19:43:28 +10:00
TroubleElectrical 9d0c7011ce Updated ALU (Q4) with 7seg and confirmed operation on board 2026-09-15 19:05:04 +10:00
TroubleElectrical 9e5fb6f52b Updated ASU (Q3) to utilise the 7seg for output, confirmed operation of Q1 to Q3 on board 2026-09-15 16:52:48 +10:00
TroubleElectrical 05361dcf70 Added all Testbenches to Modelsim and confirmed working operation 2026-09-15 15:15:00 +10:00
riley c4ebde7692 Updated ASU to use an explicit MUX rather than the XOR inversion 'trick' when calculating the operand 2026-09-14 00:13:17 +10:00
riley 4df723318b Ensured case variable assignment is internally consistent with other possibilities to ensure optimal case synthesis 2026-09-13 23:53:47 +10:00