TroubleElectrical/FPGA_Uni
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TroubleElectrical 00167dabc8 Updated ModelSim Files
2026-09-16 10:15:08 +10:00
ModelSim
Updated ModelSim Files
2026-09-16 10:15:08 +10:00
modules
Updated ALU and ASU modules to conditionally require seven-segment output logic. Used for the assignment 1 demo and MUST be stripped for assignment 2.
2026-09-15 21:27:04 +10:00
Quartus
Updated ModelSim Files
2026-09-16 10:15:08 +10:00
Submission
Added python script for invoking icarus verilog. This script has three subcommands; submit, test_submit and test. test is equivalent to the run.bat shell script, submit generates a single-file verilog source suitable for submission. test_submit will run all generated submission testbenches to verify that nothing was broken.
2026-09-15 22:00:02 +10:00
tests
Updated shifter testbench to work with 2^n widths rather than bitwidths.
2026-09-15 21:29:47 +10:00
.gitignore
Created general project structure. Only seven segment, logic unit and adder/subtractor modules and tests implemented
2026-09-03 15:25:07 +10:00
isv.py
Added python script for invoking icarus verilog. This script has three subcommands; submit, test_submit and test. test is equivalent to the run.bat shell script, submit generates a single-file verilog source suitable for submission. test_submit will run all generated submission testbenches to verify that nothing was broken.
2026-09-15 22:00:02 +10:00
README.md
Initial commit
2026-09-03 15:04:27 +10:00
run.bat
Fixed bug where includes still refered to verilog rather than systemverilog. Inverted test cases in seven segment test bench to reflect changes made to module. There is still a bug with the module where it outputs garbage
2026-09-03 16:32:56 +10:00

README.md

FPGA_Uni

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