This website requires JavaScript.
Explore
Help
Sign In
TroubleElectrical
/
FPGA_Uni
Watch
1
Star
0
Fork
0
Code
Issues
1
Pull Requests
Actions
Packages
Projects
Releases
Wiki
Activity
48
Commits
2
Branches
0
Tags
13f34e62c64bd037d8f8c5e4a0ba8b72288ad8e6
T
Code
Clone
HTTPS
Tea CLI
Open with VS Code
Open with VSCodium
Open with Intellij IDEA
Download ZIP
Download TAR.GZ
Download BUNDLE
TroubleElectrical
13f34e62c6
Added Q4 sumbission and comments
2026-09-16 12:50:58 +10:00
ModelSim
Updated ModelSim Files
2026-09-16 10:15:08 +10:00
modules
Added Q4 sumbission and comments
2026-09-16 12:50:58 +10:00
Quartus
Added comments to Q1 code and made submission file
2026-09-16 10:33:08 +10:00
Submission
Added Q4 sumbission and comments
2026-09-16 12:50:58 +10:00
tests
Added comments to Logic Unit (Q2) and added to submission file
2026-09-16 12:38:06 +10:00
.gitignore
Created general project structure. Only seven segment, logic unit and adder/subtractor modules and tests implemented
2026-09-03 15:25:07 +10:00
isv.py
Added python script for invoking icarus verilog. This script has three subcommands; submit, test_submit and test. test is equivalent to the run.bat shell script, submit generates a single-file verilog source suitable for submission. test_submit will run all generated submission testbenches to verify that nothing was broken.
2026-09-15 22:00:02 +10:00
README.md
Initial commit
2026-09-03 15:04:27 +10:00
run.bat
Fixed bug where includes still refered to verilog rather than systemverilog. Inverted test cases in seven segment test bench to reflect changes made to module. There is still a bug with the module where it outputs garbage
2026-09-03 16:32:56 +10:00
README.md
FPGA_Uni
Reference in new issue
View Git Blame
Copy Permalink
S
Description
No description provided
Readme
126
MiB
0
Stars
1
Watchers
0
Forks
Languages
SystemVerilog
85.1%
HTML
4.9%
Assembly
4.9%
Scilab
2.5%
Python
2.1%
Other
0.4%
