This website requires JavaScript.
Explore
Help
Sign In
TroubleElectrical
/
FPGA_Uni
Watch
1
Star
0
Fork
0
Code
Issues
1
Pull Requests
Actions
Packages
Projects
Releases
Wiki
Activity
54
Commits
2
Branches
0
Tags
3145dd6a216ff0a6e3d9160dbc0e970507260c5c
T
Code
Clone
HTTPS
Tea CLI
Open with VS Code
Open with VSCodium
Open with Intellij IDEA
Download ZIP
Download TAR.GZ
Download BUNDLE
TroubleElectrical
3145dd6a21
Added ROM file from MIPS Architecture Slide Part 1
2026-10-06 16:03:03 +11:00
ModelSim
Updated ModelSim Files
2026-09-16 10:15:08 +10:00
modules
Added ROM file from MIPS Architecture Slide Part 1
2026-10-06 16:03:03 +11:00
Quartus
Removed seven segment code from alu and asu
2026-09-24 15:37:48 +10:00
Submission
Added attribution to submission files
2026-09-16 13:35:35 +10:00
tests
Added comments to Logic Unit (Q2) and added to submission file
2026-09-16 12:38:06 +10:00
.gitignore
Created general project structure. Only seven segment, logic unit and adder/subtractor modules and tests implemented
2026-09-03 15:25:07 +10:00
isv.py
Added python script for invoking icarus verilog. This script has three subcommands; submit, test_submit and test. test is equivalent to the run.bat shell script, submit generates a single-file verilog source suitable for submission. test_submit will run all generated submission testbenches to verify that nothing was broken.
2026-09-15 22:00:02 +10:00
README.md
Initial commit
2026-09-03 15:04:27 +10:00
run.bat
Fixed bug where includes still refered to verilog rather than systemverilog. Inverted test cases in seven segment test bench to reflect changes made to module. There is still a bug with the module where it outputs garbage
2026-09-03 16:32:56 +10:00
README.md
FPGA_Uni
Reference in new issue
View Git Blame
Copy Permalink
S
Description
No description provided
Readme
126
MiB
0
Stars
1
Watchers
0
Forks
Languages
SystemVerilog
85.1%
HTML
4.9%
Assembly
4.9%
Scilab
2.5%
Python
2.1%
Other
0.4%
