TroubleElectrical/FPGA_Uni
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Author SHA1 Message Date
riley 76cd7931b6 Realized that, while the assembled is not binary, it is still loadable by verilog. 2026-10-08 14:18:11 +11:00
riley 0ef2aeeb48 Added instruction counter and register file 2026-10-08 14:13:38 +11:00
riley 5cb48095ce Merge branch 'main' of https://git.rileyk.au/TroubleElectrical/FPGA_Uni 2026-10-08 14:12:56 +11:00
riley aab18425f9 Added test assembly code 2026-10-08 14:08:35 +11:00
riley 3af4bfc875 Added attribution to submission files 2026-09-16 13:35:35 +10:00
riley 900b544bc6 Added python script for invoking icarus verilog. This script has three subcommands; submit, test_submit and test. test is equivalent to the run.bat shell script, submit generates a single-file verilog source suitable for submission. test_submit will run all generated submission testbenches to verify that nothing was broken. 
Renamed submission folder to fix typo.
 2026-09-15 22:00:02 +10:00
riley 6a518dcd42 Merge branch 'main' of ssh://git.rileyk.au:19482/TroubleElectrical/FPGA_Uni 
Merged incomming changes
 2026-09-15 21:29:54 +10:00
riley 392f1f7a27 Updated shifter testbench to work with 2^n widths rather than bitwidths. 2026-09-15 21:29:47 +10:00
riley 287fc1903d Updated default ASU testbench width to be 4-bit to align with seven segment width for demo 2026-09-15 21:28:01 +10:00
riley 19cd7ac177 Updated ALU and ASU modules to conditionally require seven-segment output logic. Used for the assignment 1 demo and MUST be stripped for assignment 2. 2026-09-15 21:27:04 +10:00
riley c4ebde7692 Updated ASU to use an explicit MUX rather than the XOR inversion 'trick' when calculating the operand 2026-09-14 00:13:17 +10:00
riley 4df723318b Ensured case variable assignment is internally consistent with other possibilities to ensure optimal case synthesis 2026-09-13 23:53:47 +10:00
riley 49f539c855 Updated instruction classifier to use combinational logic with a depth of 3 gates (AND, XNOR, HAND) 2026-09-13 23:35:05 +10:00
riley 19ba1bf473 Added header guards to prevent errors from double-inclusions 2026-09-13 23:09:08 +10:00
riley 78efccfe1e Implemented ALU test cases for all operations. Added ALU testbench to active testing. Fixed bug where alu_flags module argument was defined as a 2-element logic array output rather than a 2-bit logic output 2026-09-13 23:08:07 +10:00
riley f69f87ccab Just add cases for ALU testbench. The structure of the ALU testbench is now implemented. 2026-09-10 15:57:56 +10:00
riley cd7074a78c Need to change instruction classifier implementation to use a more parallel architecture as case statements can produce sequential MUX'es 2026-09-10 15:56:59 +10:00
riley 37644c629e Fixed bug of confuddling width with 2^n and w. 2026-09-10 15:42:50 +10:00
riley e9feb3cb8d Merge branch 'main' of ssh://git.rileyk.au:19482/TroubleElectrical/FPGA_Uni 2026-09-10 15:38:50 +10:00
riley 669357ccc0 Implemented ALU. Still needs testbench and testing done. 2026-09-10 15:38:36 +10:00
riley 5acf1c8b87 Fixed bug in adder/subtracter where code assuming width was the bit width was not updated when moving to the 2**N approach required by the assignment. Updated adder/subtracter testbench to correctly instantiate the asser/subtracter and removed unused variable 2026-09-08 22:49:22 +10:00
riley 42f4e661dc Implemented shifter and its test bench code fully 2026-09-08 22:35:14 +10:00
riley 9794f26137 Fixed error in logic unit testbench where it didn't instansiate the DUT at all as well as some faulty test cases and reset logic 2026-09-08 22:00:07 +10:00
riley fabfba7bdd Removed debug statement from instruction classifier testbench 2026-09-08 21:44:36 +10:00
riley f5a2455849 Added testbench for instruction classifier and fixed compilation errors. Should be fine to synthesise but icarus does not like the constant bit extraction in the always_comb block for some reason. 2026-09-08 21:31:18 +10:00
riley 00d9e3de88 Fixed error where assignment was not within a combinational/sequential block 2026-09-08 18:23:27 +10:00
riley b926d71523 Updated seven segment test bench to reflect prior commit 2026-09-03 16:58:11 +10:00
riley 3e8aa911ce Made RSIOut the LSB to correspond with wiring configuration 2026-09-03 16:56:11 +10:00
riley dd5d044da3 Fixed bit ordering in seven segment truth table and test bench 2026-09-03 16:49:46 +10:00
riley a89a66d34d Fixed bug where includes still refered to verilog rather than systemverilog. Inverted test cases in seven segment test bench to reflect changes made to module. There is still a bug with the module where it outputs garbage 2026-09-03 16:32:56 +10:00
riley f881a4126b Inverted seven segment decoder to reflect the common anode 2026-09-03 16:27:01 +10:00
riley 6668969b03 Made it clear that we are using SystemVerilog by renaming HDL files to end in .sv rather than .v 2026-09-03 16:05:52 +10:00
riley 0c21734447 Created general project structure. Only seven segment, logic unit and adder/subtractor modules and tests implemented 2026-09-03 15:25:07 +10:00