TroubleElectrical/FPGA_Uni
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26 Commits
Author SHA1 Message Date
riley 38fa35fccd Fixed initialisation bug and compilation error in gatereg module. Added mips_pipelined to test suite. Fixed several bugs in assignment3 MIPS module 2026-11-05 14:10:13 +11:00
riley 704286f0e6 Renamed MIPS test to be a single cycle test 2026-11-04 15:42:52 +11:00
riley b52f01c3be Added some delay to better test final branch/halt. 2026-10-20 16:02:40 +11:00
riley 2f652705cc Fixed timing in testbench for branch iteration. 2026-10-16 12:51:21 +11:00
riley e7fff9f3dc Added explicit rst input to RAM and PC as well as the MIPS processor. 2026-10-16 12:11:19 +11:00
riley 559ff01d69 Fixed printing annoyance. Added variable dumping to a wavefile. Updated delay to 2 units (as there is 1 unit of clk being high and 1 unit low). 
Removed register initialisation code from testbench.
Fixed typo when wanting to check T0 (R8) but was checking R0.
Added explicit if-else begin-end blocks to logging and a simulation exit when the testbench is done.
 2026-10-16 11:41:33 +11:00
riley 19e5843d55 Added testbench for MIPS processor 2026-10-16 03:53:14 +11:00
riley 1e13de9301 Updated assignment2. Created file for testing R-type instructions, still needs to be implemented. Consider using bind to be able to extract inner-scoped variables out for inspection. 2026-10-13 22:26:52 +11:00
riley 75ef513efa Added zero flag to ALU and updated testbench to not fail because of it. TODO: Add cases to test the zero flag 2026-10-13 21:34:25 +11:00
TroubleElectrical 56ade6b426 Added comments to Logic Unit (Q2) and added to submission file 2026-09-16 12:38:06 +10:00
riley 392f1f7a27 Updated shifter testbench to work with 2^n widths rather than bitwidths. 2026-09-15 21:29:47 +10:00
riley 287fc1903d Updated default ASU testbench width to be 4-bit to align with seven segment width for demo 2026-09-15 21:28:01 +10:00
riley 49f539c855 Updated instruction classifier to use combinational logic with a depth of 3 gates (AND, XNOR, HAND) 2026-09-13 23:35:05 +10:00
riley 78efccfe1e Implemented ALU test cases for all operations. Added ALU testbench to active testing. Fixed bug where alu_flags module argument was defined as a 2-element logic array output rather than a 2-bit logic output 2026-09-13 23:08:07 +10:00
riley f69f87ccab Just add cases for ALU testbench. The structure of the ALU testbench is now implemented. 2026-09-10 15:57:56 +10:00
riley 5acf1c8b87 Fixed bug in adder/subtracter where code assuming width was the bit width was not updated when moving to the 2**N approach required by the assignment. Updated adder/subtracter testbench to correctly instantiate the asser/subtracter and removed unused variable 2026-09-08 22:49:22 +10:00
riley 42f4e661dc Implemented shifter and its test bench code fully 2026-09-08 22:35:14 +10:00
riley 9794f26137 Fixed error in logic unit testbench where it didn't instansiate the DUT at all as well as some faulty test cases and reset logic 2026-09-08 22:00:07 +10:00
riley fabfba7bdd Removed debug statement from instruction classifier testbench 2026-09-08 21:44:36 +10:00
riley f5a2455849 Added testbench for instruction classifier and fixed compilation errors. Should be fine to synthesise but icarus does not like the constant bit extraction in the always_comb block for some reason. 2026-09-08 21:31:18 +10:00
TroubleElectrical 60e5dae43b Added ModelSim folder (and have to add files into it as to allow for different testbench code) 2026-09-08 16:32:01 +10:00
riley b926d71523 Updated seven segment test bench to reflect prior commit 2026-09-03 16:58:11 +10:00
riley dd5d044da3 Fixed bit ordering in seven segment truth table and test bench 2026-09-03 16:49:46 +10:00
riley a89a66d34d Fixed bug where includes still refered to verilog rather than systemverilog. Inverted test cases in seven segment test bench to reflect changes made to module. There is still a bug with the module where it outputs garbage 2026-09-03 16:32:56 +10:00
riley 6668969b03 Made it clear that we are using SystemVerilog by renaming HDL files to end in .sv rather than .v 2026-09-03 16:05:52 +10:00
riley 0c21734447 Created general project structure. Only seven segment, logic unit and adder/subtractor modules and tests implemented 2026-09-03 15:25:07 +10:00