riley fabfba7bdd Removed debug statement from instruction classifier testbench

2026-09-08 21:44:36 +10:00

..

alu_tb.sv

Fixed bug where includes still refered to verilog rather than systemverilog. Inverted test cases in seven segment test bench to reflect changes made to module. There is still a bug with the module where it outputs garbage

2026-09-03 16:32:56 +10:00

asu_tb.sv

Fixed bug where includes still refered to verilog rather than systemverilog. Inverted test cases in seven segment test bench to reflect changes made to module. There is still a bug with the module where it outputs garbage

2026-09-03 16:32:56 +10:00

instruction_classifier_tb.sv

Removed debug statement from instruction classifier testbench

2026-09-08 21:44:36 +10:00

lu_tb.sv

Added ModelSim folder (and have to add files into it as to allow for different testbench code)

2026-09-08 16:32:01 +10:00

lu_tb.sv.bak

Added ModelSim folder (and have to add files into it as to allow for different testbench code)

2026-09-08 16:32:01 +10:00

seven_seg_tb.sv

Updated seven segment test bench to reflect prior commit

2026-09-03 16:58:11 +10:00

shifter_tb.sv

Fixed bug where includes still refered to verilog rather than systemverilog. Inverted test cases in seven segment test bench to reflect changes made to module. There is still a bug with the module where it outputs garbage

2026-09-03 16:32:56 +10:00

tests.sv

Added testbench for instruction classifier and fixed compilation errors. Should be fine to synthesise but icarus does not like the constant bit extraction in the always_comb block for some reason.

2026-09-08 21:31:18 +10:00