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Created general project structure. Only seven segment, logic unit and adder/subtractor modules and tests implemented

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riley committed 2026-09-03 15:25:07 +10:00
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tests/alu_tb.v
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// TODO: Both the ALU and this test bench is incomplete
`#include "alu.v"
module alu_tb #(width=8)();
endmodule
tests/asu_tb.v
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`include "asu.v"
module asu_tb #(width=8)();
logic [0:0] op;
logic [width-1:0] A;
logic [width-1:0] B;
logic [width-1:0] C;
logic [0:0] Cout;
logic [0:0] Cin;
logic [width-1:0] C_exp;
logic [0:0] Cout_exp;
logic [0:0] Cin_exp; // TODO
logic [0:0] Signed_overflow;
asu #(width) dut(op, A, B, C, Cout, Cin);
integer error_count;
initial begin
error_count = 0;
$display("Beginning ASU tests");
// Test basic addition of 0+1 = 1
op = 1'b0;
A = {width{1'b0}};
B = { {(width-1){1'b0}}, 1'b1};
C_exp = { {(width-1){1'b0}}, 1'b1};
Cout_exp = 1'b0;
Cin_exp = 1'b0;
#1;
if (C != C_exp || Cout != Cout_exp || Cin != Cin_exp || (Cin ^ Cout) != (Cin_exp ^ Cout_exp)) begin
$display("\t\x1b[38;5;9mOp 0b%b(0b%b, 0b%b) produced 0b%b%b_%b but 0b%b%b_%b was expected\x1b[m", op, A, B, Cin, Cout, C, Cin_exp, Cout_exp, C_exp);
error_count = error_count + 1;
end
// Test underflow from 0-1 = UINTMAX
op = 1'b1;
C_exp = {(width){1'b1}};
Cout_exp = 1'b0;
Cin_exp = 1'b0;
#1;
if (C != C_exp || Cout != Cout_exp || Cin != Cin_exp || (Cin ^ Cout) != (Cin_exp ^ Cout_exp)) begin
$display("\t\x1b[38;5;9mOp 0b%b(0b%b, 0b%b) produced 0b%b%b_%b but 0b%b%b_%b was expected\x1b[m", op, A, B, Cin, Cout, C, Cin_exp, Cout_exp, C_exp);
error_count = error_count + 1;
end
// Test carry addition of 1+1 = 2
op = 1'b0;
A = { {(width-1){1'b0}}, 1'b1};
B = { {(width-1){1'b0}}, 1'b1};
C_exp = { {(width-2){1'b0}}, 2'b10};
Cout_exp = 1'b0;
Cin_exp = 1'b0;
#1;
if (C != C_exp || Cout != Cout_exp || Cin != Cin_exp || (Cin ^ Cout) != (Cin_exp ^ Cout_exp)) begin
$display("\t\x1b[38;5;9mOp 0b%b(0b%b, 0b%b) produced 0b%b%b_%b but 0b%b%b_%b was expected\x1b[m", op, A, B, Cin, Cout, C, Cin_exp, Cout_exp, C_exp);
error_count = error_count + 1;
end
// Test overflow from UINTMAX+1 = 0
A = {(width){1'b1}}; // UINTMAX
B = { {(width-1){1'b0}}, 1'b1}; // 1
C_exp = {(width){1'b0}};
Cout_exp = 1'b1;
Cin_exp = 1'b1;
#1;
if (C != C_exp || Cout != Cout_exp || Cin != Cin_exp || (Cin ^ Cout) != (Cin_exp ^ Cout_exp)) begin
$display("\t\x1b[38;5;9mOp 0b%b(0b%b, 0b%b) produced 0b%b%b_%b but 0b%b%b_%b was expected\x1b[m", op, A, B, Cin, Cout, C, Cin_exp, Cout_exp, C_exp);
error_count = error_count + 1;
end
// Tests INTMAX+1
op = 1'b0;
A = {1'b0, {(width-1){1'b1}}}; // INTMAX
B = {{(width-1){1'b0}}, 1'b1}; // 1
C_exp = {1'b1, {(width-1){1'b0}}}; // -INTMAX
Cin_exp = 1'b1;
Cout_exp = 1'b0;
#1;
if (C != C_exp || Cout != Cout_exp || Cin != Cin_exp || (Cin ^ Cout) != (Cin_exp ^ Cout_exp)) begin
$display("\t\x1b[38;5;9mOp 0b%b(0b%b, 0b%b) produced 0b%b%b_%b but 0b%b%b_%b was expected\x1b[m", op, A, B, Cin, Cout, C, Cin_exp, Cout_exp, C_exp);
error_count = error_count + 1;
end
op = 1'b0;
A = {1'b1, {(width-1){1'b0}}}; // -INTMAX
B = {1'b1, {(width-1){1'b0}}}; // -INTMAX
C_exp = {width{1'b0}}; // 0
Cin_exp = 1'b0;
Cout_exp = 1'b1;
#1;
if (C != C_exp || Cout != Cout_exp || Cin != Cin_exp || (Cin ^ Cout) != (Cin_exp ^ Cout_exp)) begin
$display("\t\x1b[38;5;9mOp 0b%b(0b%b, 0b%b) produced 0b%b%b_%b but 0b%b%b_%b was expected\x1b[m", op, A, B, Cin, Cout, C, Cin_exp, Cout_exp, C_exp);
error_count = error_count + 1;
end
op = 1'b1;
A = {1'b0, {(width-1){1'b1}}}; // INTMAX
B = {1'b1, {(width-1){1'b0}}}; // -INTMAX
C_exp = {width{1'b1}}; // -1
Cin_exp = 1'b1;
Cout_exp = 1'b0;
#1;
if (C != C_exp || Cout != Cout_exp || Cin != Cin_exp || (Cin ^ Cout) != (Cin_exp ^ Cout_exp)) begin
$display("\t\x1b[38;5;9mOp 0b%b(0b%b, 0b%b) produced 0b%b%b_%b but 0b%b%b_%b was expected\x1b[m", op, A, B, Cin, Cout, C, Cin_exp, Cout_exp, C_exp);
error_count = error_count + 1;
end
op = 1'b1;
A = {1'b1, {(width-1){1'b0}}}; // -INTMAX
B = {{(width-1){1'b0}}, 1'b1}; // 1
C_exp = {1'b0, {(width-1){1'b1}}}; // INTMAX
Cin_exp = 1'b0;
Cout_exp = 1'b1;
#1;
if (C != C_exp || Cout != Cout_exp || Cin != Cin_exp || (Cin ^ Cout) != (Cin_exp ^ Cout_exp)) begin
$display("\t\x1b[38;5;9mOp 0b%b(0b%b, 0b%b) produced 0b%b%b_%b but 0b%b%b_%b was expected\x1b[m", op, A, B, Cin, Cout, C, Cin_exp, Cout_exp, C_exp);
error_count = error_count + 1;
end
if (error_count == 0) $display("\x1b[38;5;10mAll ASU tests passing\x1b[m");
else $display("\x1b[38;5;9m%0d ASU test(s) failing\x1b[m", error_count);
end
endmodule
tests/instruction_classifier_tb.v
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`#include "instruction_classifier.v"
tests/lu_tb.v
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`include "lu.v"
module lu_tb #(W=8)();
logic [1:0] op;
logic [W-1:0] A;
logic [W-1:0] B;
logic [W-1:0] C;
logic [W-1:0] C_exp[16];
lu #(W) dut();
integer error_count;
initial begin
// AND
C_exp[0] = {W{1'b0}};
C_exp[1] = {W{1'b0}};
C_exp[2] = {W{1'b0}};
C_exp[3] = {W{1'b0}};
// OR
C_exp[4] = {W{1'b0}};
C_exp[5] = {W{1'b1}};
C_exp[6] = {W{1'b1}};
C_exp[7] = {W{1'b1}};
// XOR
C_exp[8] = {W{1'b0}};
C_exp[9] = {W{1'b1}};
C_exp[10] = {W{1'b1}};
C_exp[11] = {W{1'b0}};
// NOR
C_exp[12] = {W{1'b1}};
C_exp[13] = {W{1'b0}};
C_exp[14] = {W{1'b0}};
C_exp[15] = {W{1'b0}};
error_count = 0;
op = 0;
A = 0;
B = 0;
$display("Beginning LU tests");
for (integer N = 0; N < 4; ++N) begin
for (integer M = 0; M < 2; ++M) begin
for (integer K = 0; K < 2; ++K) begin
#1;
if (C != C_exp[N*2*2 + M*2 + K]) begin
$display("\t\x1b[38;5;9mOp 0b%b(0b%b, 0b%b) produced 0b%b but 0b%b was expected\x1b[m", op, A, B, C, C_exp[N*2*2 + M*2 + K]);
error_count = error_count + 1;
end
B = 1;
end
A = 1;
end
A = 0;
B = 0;
op = op + 1;
end
if (error_count == 0) $display("\x1b[38;5;10mAll LU tests passing\x1b[m");
else $display("\x1b[38;5;9m%0d LU test(s) failing\x1b[m", error_count);
end
endmodule
tests/seven_seg_tb.v
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`include "seven_seg.v"
module seven_seg_tb();
logic [3:0] in_num;
logic [0:0] in_rbi_inv;
logic [7:0] out_segments;
logic [7:0] true_segments[17];
seven_seg dut(in_num, in_rbi_inv, out_segments);
integer N;
integer i;
integer error_count;
initial begin
// Initialise truth table
true_segments[0 ] = 8'b11111101;
true_segments[1 ] = 8'b01100001;
true_segments[2 ] = 8'b11011011;
true_segments[3 ] = 8'b11110011;
true_segments[4 ] = 8'b01100111;
true_segments[5 ] = 8'b10110111;
true_segments[6 ] = 8'b10111111;
true_segments[7 ] = 8'b11100001;
true_segments[8 ] = 8'b11111111;
true_segments[9 ] = 8'b11100111;
true_segments[10] = 8'b11101111;
true_segments[11] = 8'b00111111;
true_segments[12] = 8'b10011101;
true_segments[13] = 8'b01111011;
true_segments[14] = 8'b10011111;
true_segments[15] = 8'b10001111;
true_segments[16] = 8'b00000000;
$display("Beginning seven-segment tests");
in_num = 4'd0;
in_rbi_inv = 1'b0;
error_count = 0;
#1;
if (out_segments !== true_segments[16]) begin
$display("\t\x1b[38;5;9mNumber 0b%b failed to decode to 0b%b, producing 0b%b\x1b[m", in_num, true_segments[16], out_segments);
error_count = error_count + 1;
end
for (N=1; N < 15; ++N) begin
in_num = in_num + 1;
#1;
if (out_segments !== true_segments[N]) begin
$display("\t\x1b[38;5;9mNumber 0b%b failed to decode to 0b%b, producing 0b%b\x1b[m", in_num, true_segments[N], out_segments);
error_count = error_count + 1;
end
end
in_num = 4'd0;
in_rbi_inv = 1'b1;
for (N=0; N < 15; ++N) begin
#1;
if (out_segments !== true_segments[N]) begin
$display("\t\x1b[38;5;9mNumber 0b%b failed to decode to 0b%b, producing 0b%b\x1b[m", in_num, true_segments[N], out_segments);
error_count = error_count + 1;
end
in_num = in_num + 1;
end
if (error_count == 0) $display("\x1b[38;5;10mAll seven-segment tests passing\x1b[m");
else $display("\x1b[38;5;9m%0d seven-segment test(s) failing\x1b[m", error_count);
end
endmodule
tests/shifter_tb.v
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`#include "shifter.v"
module shifter_tb #(width=8)();
endmodule
tests/tests.v
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`include "tests/seven_seg_tb.v"
`include "tests/lu_tb.v"
`include "tests/asu_tb.v"