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Fixed initialisation bug and compilation error in gatereg module. Added mips_pipelined to test suite. Fixed several bugs in assignment3 MIPS module

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riley committed 2026-11-05 14:10:13 +11:00
1 parent cc98bfbf02
commit 38fa35fccd
4 files changed
+155 -30
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tests/mips_pipelined.sv
+118
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@@ -0,0 +1,118 @@
`include "assignment3.sv"
`timescale 1us/10ns
`define PRINT_REGISTERS(regs)\
$display("\tt0-t8: \t0x%0x 0x%0x 0x%0x 0x%0x 0x%0x 0x%0x 0x%0x 0x%0x\n\ts0-s8: \t0x%0x 0x%0x 0x%0x 0x%0x 0x%0x 0x%0x 0x%0x 0x%0x\n",\
regs[8], regs[9], regs[10], regs[11], regs[12], regs[13], regs[14], regs[15], \
regs[16], regs[17], regs[18], regs[19], regs[20], regs[21], regs[22], regs[23] \
);
`define TEST_CHECK(cond) if (cond) begin end else begin \
$display("Check %s failed", `"cond`"); \
`PRINT_REGISTERS(CPU.REGS.regs); \
num_errors += 1; \
end
module mips_pipelined_tb();
logic [0:0] clk;
logic [0:0] rst;
assignment3 CPU (clk, rst);
initial clk = 0;
initial rst = 0;
always #1 clk = ~clk;
integer num_errors = 0;
initial begin
rst = 1;
#2;
rst = 0;
#2;
$display("Beginning Pipelined MIPS tests");
#8; // 4x steps to allow pipeline to fill up
`TEST_CHECK(CPU.REGS.regs[8] == 32'd0);
#2;
`TEST_CHECK(CPU.REGS.regs[9] == 32'd0);
#2;
`TEST_CHECK(CPU.REGS.regs[10] == 32'd0);
#2;
`TEST_CHECK(CPU.REGS.regs[11] == 32'd0);
#2;
`TEST_CHECK(CPU.REGS.regs[9] == 32'd7);
#2;
`TEST_CHECK(CPU.RAM.mem[0] == 32'd7);
#2;
`TEST_CHECK(CPU.REGS.regs[10] == 32'd0);
#2;
`TEST_CHECK(CPU.REGS.regs[11] == 32'd0);
#2;
`TEST_CHECK(CPU.REGS.regs[12] == 32'd0);
#2;
`TEST_CHECK(CPU.REGS.regs[10] == 32'd7);
#2;
`TEST_CHECK(CPU.REGS.regs[11] == 32'd0);
#2;
`TEST_CHECK(CPU.REGS.regs[12] == 32'd0);
#2;
`TEST_CHECK(CPU.REGS.regs[13] == 32'd0);
#2;
`TEST_CHECK(CPU.REGS.regs[11] == (CPU.REGS.regs[10] + CPU.REGS.regs[11]) );
`TEST_CHECK(CPU.REGS.regs[11] == 32'd14);
#2;
`TEST_CHECK(CPU.REGS.regs[12] == 32'd0);
#2;
`TEST_CHECK(CPU.REGS.regs[13] == 32'd0);
#2;
`TEST_CHECK(CPU.REGS.regs[14] == 32'd0);
#2;
`TEST_CHECK(CPU.REGS.regs[12] == (CPU.REGS.regs[9] - CPU.REGS.regs[11]));
`TEST_CHECK(CPU.REGS.regs[12] == -32'sd7);
#2;
`TEST_CHECK(CPU.REGS.regs[13] == (CPU.REGS.regs[9] + 3) );
`TEST_CHECK(CPU.REGS.regs[13] == 32'd10);
#2;
`TEST_CHECK(CPU.REGS.regs[14] == 32'd0);
#2;
`TEST_CHECK(CPU.REGS.regs[15] == 32'd0);
#2;
`TEST_CHECK(CPU.REGS.regs[16] == 32'd0);
#2;
`TEST_CHECK(CPU.REGS.regs[14] == (CPU.REGS.regs[12] + CPU.REGS.regs[13]));
`TEST_CHECK(CPU.REGS.regs[14] == 32'd3);
#2;
`TEST_CHECK(CPU.REGS.regs[16] == (CPU.REGS.regs[9] & CPU.REGS.regs[13]));
`TEST_CHECK(CPU.REGS.regs[16] == 32'd2);
#2;
`TEST_CHECK(CPU.REGS.regs[17] == (CPU.REGS.regs[9] | CPU.REGS.regs[13]));
`TEST_CHECK(CPU.REGS.regs[17] == 32'd15);
#2;
`TEST_CHECK(CPU.REGS.regs[18] == (CPU.REGS.regs[9] ^ CPU.REGS.regs[13]));
`TEST_CHECK(CPU.REGS.regs[18] == 32'd13);
#2;
`TEST_CHECK(CPU.REGS.regs[19] == ~(CPU.REGS.regs[9] | CPU.REGS.regs[13]));
`TEST_CHECK(CPU.REGS.regs[19] == 32'hfffffff0);
#2;
`TEST_CHECK(CPU.REGS.regs[20] == ( $signed(CPU.REGS.regs[12]) < $signed(CPU.REGS.regs[14]) ));
`TEST_CHECK(CPU.REGS.regs[20] == 32'd1);
#2;
`TEST_CHECK(CPU.REGS.regs[20] == ( CPU.REGS.regs[12] < CPU.REGS.regs[14] ));
`TEST_CHECK(CPU.REGS.regs[20] == 32'd0);
// TODO: Verify program never branches
#2;
#2;
#2;
#2;
// TODO: Verify final program register state
if (num_errors == 0) begin $display("\x1b[38;5;10mAll pipelined MIPS tests passing\x1b[m");
end else begin $display("\x1b[38;5;9m%0d Single-cycle pipelined test(s) failing\x1b[m", num_errors); end
$dumpflush;
$finish;
end
endmodule
tests/tests.sv
+2 -1
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@@ -4,4 +4,5 @@
`include "tests/instruction_classifier_tb.sv"
`include "tests/shifter_tb.sv"
`include "tests/alu_tb.sv"
`include "tests/mips_singlecycle.sv"
`include "tests/mips_singlecycle.sv"
`include "tests/mips_pipelined.sv"