Added explicit rst input to RAM and PC as well as the MIPS processor.

tests/mips.sv

@@ -15,13 +15,20 @@
 
 module mips_tb();
     logic [0:0] clk;
-    assignment2 #(5) CPU (clk);
+    logic [0:0] rst;
+    assignment2 #(5) CPU (clk, rst);
 
     initial clk = 0;
+    initial rst = 0;
     always #1 clk = ~clk;
 
     integer num_errors = 0;
     initial begin
+        rst = 1;
+        #2;
+        rst = 0;
+        #2;
+        
         $dumpfile("output.vcd");
 		$dumpvars(0, clk);
 		$dumpvars(1, CPU.REGS);
@@ -31,6 +38,7 @@ module mips_tb();
 		$dumpvars(5, CPU.CONTROL_UNIT);
 		$dumpvars(5, CPU.instruction);
 		$dumpvars(5, CPU.ALU);
+		$dumpvars(6, CPU.flags);
 
         // Zero out lower registers
         $display("Beginning MIPS tests");