riley 392f1f7a27 Updated shifter testbench to work with 2^n widths rather than bitwidths.

2026-09-15 21:29:47 +10:00

..

alu_tb.sv

Implemented ALU test cases for all operations. Added ALU testbench to active testing. Fixed bug where alu_flags module argument was defined as a 2-element logic array output rather than a 2-bit logic output

2026-09-13 23:08:07 +10:00

asu_tb.sv

Updated default ASU testbench width to be 4-bit to align with seven segment width for demo

2026-09-15 21:28:01 +10:00

instruction_classifier_tb.sv

Updated instruction classifier to use combinational logic with a depth of 3 gates (AND, XNOR, HAND)

2026-09-13 23:35:05 +10:00

lu_tb.sv

Fixed error in logic unit testbench where it didn't instansiate the DUT at all as well as some faulty test cases and reset logic

2026-09-08 22:00:07 +10:00

lu_tb.sv.bak

Added ModelSim folder (and have to add files into it as to allow for different testbench code)

2026-09-08 16:32:01 +10:00

seven_seg_tb.sv

Updated seven segment test bench to reflect prior commit

2026-09-03 16:58:11 +10:00

shifter_tb.sv

Updated shifter testbench to work with 2^n widths rather than bitwidths.

2026-09-15 21:29:47 +10:00

tests.sv

Implemented ALU test cases for all operations. Added ALU testbench to active testing. Fixed bug where alu_flags module argument was defined as a 2-element logic array output rather than a 2-bit logic output

2026-09-13 23:08:07 +10:00