riley 6668969b03 Made it clear that we are using SystemVerilog by renaming HDL files to end in .sv rather than .v

2026-09-03 16:05:52 +10:00

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alu_tb.sv

Made it clear that we are using SystemVerilog by renaming HDL files to end in .sv rather than .v

2026-09-03 16:05:52 +10:00

asu_tb.sv

Made it clear that we are using SystemVerilog by renaming HDL files to end in .sv rather than .v

2026-09-03 16:05:52 +10:00

instruction_classifier_tb.sv

Made it clear that we are using SystemVerilog by renaming HDL files to end in .sv rather than .v

2026-09-03 16:05:52 +10:00

lu_tb.sv

Made it clear that we are using SystemVerilog by renaming HDL files to end in .sv rather than .v

2026-09-03 16:05:52 +10:00

seven_seg_tb.sv

Made it clear that we are using SystemVerilog by renaming HDL files to end in .sv rather than .v

2026-09-03 16:05:52 +10:00

shifter_tb.sv

Made it clear that we are using SystemVerilog by renaming HDL files to end in .sv rather than .v

2026-09-03 16:05:52 +10:00

tests.sv

Made it clear that we are using SystemVerilog by renaming HDL files to end in .sv rather than .v

2026-09-03 16:05:52 +10:00