riley dd5d044da3 Fixed bit ordering in seven segment truth table and test bench

2026-09-03 16:49:46 +10:00

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alu_tb.sv

Fixed bug where includes still refered to verilog rather than systemverilog. Inverted test cases in seven segment test bench to reflect changes made to module. There is still a bug with the module where it outputs garbage

2026-09-03 16:32:56 +10:00

asu_tb.sv

Fixed bug where includes still refered to verilog rather than systemverilog. Inverted test cases in seven segment test bench to reflect changes made to module. There is still a bug with the module where it outputs garbage

2026-09-03 16:32:56 +10:00

instruction_classifier_tb.sv

Fixed bug where includes still refered to verilog rather than systemverilog. Inverted test cases in seven segment test bench to reflect changes made to module. There is still a bug with the module where it outputs garbage

2026-09-03 16:32:56 +10:00

lu_tb.sv

Fixed bug where includes still refered to verilog rather than systemverilog. Inverted test cases in seven segment test bench to reflect changes made to module. There is still a bug with the module where it outputs garbage

2026-09-03 16:32:56 +10:00

seven_seg_tb.sv

Fixed bit ordering in seven segment truth table and test bench

2026-09-03 16:49:46 +10:00

shifter_tb.sv

Fixed bug where includes still refered to verilog rather than systemverilog. Inverted test cases in seven segment test bench to reflect changes made to module. There is still a bug with the module where it outputs garbage

2026-09-03 16:32:56 +10:00

tests.sv

Fixed bug where includes still refered to verilog rather than systemverilog. Inverted test cases in seven segment test bench to reflect changes made to module. There is still a bug with the module where it outputs garbage

2026-09-03 16:32:56 +10:00