Made it clear that we are using SystemVerilog by renaming HDL files to end in .sv rather than .v

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riley committed 2026-09-03 16:05:52 +10:00

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commit 6668969b03

13 files changed

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tests/alu_tb.v → tests/alu_tb.sv

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tests/asu_tb.v → tests/asu_tb.sv

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tests/instruction_classifier_tb.v → tests/instruction_classifier_tb.sv

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tests/lu_tb.v → tests/lu_tb.sv

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tests/seven_seg_tb.v → tests/seven_seg_tb.sv

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tests/shifter_tb.v → tests/shifter_tb.sv

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tests/tests.v → tests/tests.sv

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