Added attribution to submission files

Renamed submission folder to fix typo.

ModelSim/Assignment_1_Q1.cr.mti

@@ -0,0 +1,16 @@
+/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/seven_seg.sv {1 {vlog -work work -sv -stats=none /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/seven_seg.sv
+Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
+-- Compiling module seven_seg
+
+Top level modules:
+	seven_seg
+
+} {} {}} /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/seven_seg_tb.sv {1 {vlog -work work -sv -stats=none /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/seven_seg_tb.sv
+Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
+-- Compiling module seven_seg
+-- Compiling module seven_seg_tb
+
+Top level modules:
+	seven_seg_tb
+
+} {} {}}

ModelSim/Assignment_1_Q1.mpf

@@ -0,0 +1,466 @@
+; Copyright 1991-2009 Mentor Graphics Corporation
+;
+; All Rights Reserved.
+;
+; THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH IS THE PROPERTY OF 
+; MENTOR GRAPHICS CORPORATION OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS.
+;   
+
+[Library]
+std = $MODEL_TECH/../std
+ieee = $MODEL_TECH/../ieee
+verilog = $MODEL_TECH/../verilog
+vital2000 = $MODEL_TECH/../vital2000
+std_developerskit = $MODEL_TECH/../std_developerskit
+synopsys = $MODEL_TECH/../synopsys
+modelsim_lib = $MODEL_TECH/../modelsim_lib
+sv_std = $MODEL_TECH/../sv_std
+
+; Altera Primitive libraries
+;
+; VHDL Section
+;
+altera_mf = $MODEL_TECH/../altera/vhdl/altera_mf
+altera = $MODEL_TECH/../altera/vhdl/altera
+altera_lnsim = $MODEL_TECH/../altera/vhdl/altera_lnsim
+lpm = $MODEL_TECH/../altera/vhdl/220model
+220model = $MODEL_TECH/../altera/vhdl/220model
+maxii = $MODEL_TECH/../altera/vhdl/maxii
+maxv = $MODEL_TECH/../altera/vhdl/maxv
+fiftyfivenm = $MODEL_TECH/../altera/vhdl/fiftyfivenm
+sgate = $MODEL_TECH/../altera/vhdl/sgate
+arriaii = $MODEL_TECH/../altera/vhdl/arriaii
+arriaii_hssi = $MODEL_TECH/../altera/vhdl/arriaii_hssi
+arriaii_pcie_hip = $MODEL_TECH/../altera/vhdl/arriaii_pcie_hip
+arriaiigz = $MODEL_TECH/../altera/vhdl/arriaiigz
+arriaiigz_hssi = $MODEL_TECH/../altera/vhdl/arriaiigz_hssi
+arriaiigz_pcie_hip = $MODEL_TECH/../altera/vhdl/arriaiigz_pcie_hip
+stratixiv = $MODEL_TECH/../altera/vhdl/stratixiv
+stratixiv_hssi = $MODEL_TECH/../altera/vhdl/stratixiv_hssi
+stratixiv_pcie_hip = $MODEL_TECH/../altera/vhdl/stratixiv_pcie_hip
+cycloneiv = $MODEL_TECH/../altera/vhdl/cycloneiv
+cycloneiv_hssi = $MODEL_TECH/../altera/vhdl/cycloneiv_hssi
+cycloneiv_pcie_hip = $MODEL_TECH/../altera/vhdl/cycloneiv_pcie_hip
+cycloneive = $MODEL_TECH/../altera/vhdl/cycloneive
+stratixv = $MODEL_TECH/../altera/vhdl/stratixv
+stratixv_hssi = $MODEL_TECH/../altera/vhdl/stratixv_hssi
+stratixv_pcie_hip = $MODEL_TECH/../altera/vhdl/stratixv_pcie_hip
+arriavgz = $MODEL_TECH/../altera/vhdl/arriavgz
+arriavgz_hssi = $MODEL_TECH/../altera/vhdl/arriavgz_hssi
+arriavgz_pcie_hip = $MODEL_TECH/../altera/vhdl/arriavgz_pcie_hip
+arriav = $MODEL_TECH/../altera/vhdl/arriav
+cyclonev = $MODEL_TECH/../altera/vhdl/cyclonev
+twentynm = $MODEL_TECH/../altera/vhdl/twentynm
+twentynm_hssi = $MODEL_TECH/../altera/vhdl/twentynm_hssi
+twentynm_hip = $MODEL_TECH/../altera/vhdl/twentynm_hip
+cyclone10lp = $MODEL_TECH/../altera/vhdl/cyclone10lp
+;
+; Verilog Section
+;
+altera_mf_ver = $MODEL_TECH/../altera/verilog/altera_mf
+altera_ver = $MODEL_TECH/../altera/verilog/altera
+altera_lnsim_ver = $MODEL_TECH/../altera/verilog/altera_lnsim
+lpm_ver = $MODEL_TECH/../altera/verilog/220model
+220model_ver = $MODEL_TECH/../altera/verilog/220model
+maxii_ver = $MODEL_TECH/../altera/verilog/maxii
+maxv_ver = $MODEL_TECH/../altera/verilog/maxv
+fiftyfivenm_ver = $MODEL_TECH/../altera/verilog/fiftyfivenm
+sgate_ver = $MODEL_TECH/../altera/verilog/sgate
+arriaii_ver = $MODEL_TECH/../altera/verilog/arriaii
+arriaii_hssi_ver = $MODEL_TECH/../altera/verilog/arriaii_hssi
+arriaii_pcie_hip_ver = $MODEL_TECH/../altera/verilog/arriaii_pcie_hip
+arriaiigz_ver = $MODEL_TECH/../altera/verilog/arriaiigz
+arriaiigz_hssi_ver = $MODEL_TECH/../altera/verilog/arriaiigz_hssi
+arriaiigz_pcie_hip_ver = $MODEL_TECH/../altera/verilog/arriaiigz_pcie_hip
+stratixiv_ver = $MODEL_TECH/../altera/verilog/stratixiv
+stratixiv_hssi_ver = $MODEL_TECH/../altera/verilog/stratixiv_hssi
+stratixiv_pcie_hip_ver = $MODEL_TECH/../altera/verilog/stratixiv_pcie_hip
+stratixv_ver = $MODEL_TECH/../altera/verilog/stratixv
+stratixv_hssi_ver = $MODEL_TECH/../altera/verilog/stratixv_hssi
+stratixv_pcie_hip_ver = $MODEL_TECH/../altera/verilog/stratixv_pcie_hip
+arriavgz_ver = $MODEL_TECH/../altera/verilog/arriavgz
+arriavgz_hssi_ver = $MODEL_TECH/../altera/verilog/arriavgz_hssi
+arriavgz_pcie_hip_ver = $MODEL_TECH/../altera/verilog/arriavgz_pcie_hip
+arriav_ver = $MODEL_TECH/../altera/verilog/arriav
+arriav_hssi_ver = $MODEL_TECH/../altera/verilog/arriav_hssi
+arriav_pcie_hip_ver = $MODEL_TECH/../altera/verilog/arriav_pcie_hip
+cyclonev_ver = $MODEL_TECH/../altera/verilog/cyclonev
+cyclonev_hssi_ver = $MODEL_TECH/../altera/verilog/cyclonev_hssi
+cyclonev_pcie_hip_ver = $MODEL_TECH/../altera/verilog/cyclonev_pcie_hip
+cycloneiv_ver = $MODEL_TECH/../altera/verilog/cycloneiv
+cycloneiv_hssi_ver = $MODEL_TECH/../altera/verilog/cycloneiv_hssi
+cycloneiv_pcie_hip_ver = $MODEL_TECH/../altera/verilog/cycloneiv_pcie_hip
+cycloneive_ver = $MODEL_TECH/../altera/verilog/cycloneive
+twentynm_ver = $MODEL_TECH/../altera/verilog/twentynm
+twentynm_hssi_ver = $MODEL_TECH/../altera/verilog/twentynm_hssi
+twentynm_hip_ver = $MODEL_TECH/../altera/verilog/twentynm_hip
+cyclone10lp_ver = $MODEL_TECH/../altera/verilog/cyclone10lp
+
+work = work
+[vcom]
+; VHDL93 variable selects language version as the default. 
+; Default is VHDL-2002.
+; Value of 0 or 1987 for VHDL-1987.
+; Value of 1 or 1993 for VHDL-1993.
+; Default or value of 2 or 2002 for VHDL-2002.
+; Default or value of 3 or 2008 for VHDL-2008.
+VHDL93 = 2002
+
+; Show source line containing error. Default is off.
+; Show_source = 1
+
+; Turn off unbound-component warnings. Default is on.
+; Show_Warning1 = 0
+
+; Turn off process-without-a-wait-statement warnings. Default is on.
+; Show_Warning2 = 0
+
+; Turn off null-range warnings. Default is on.
+; Show_Warning3 = 0
+
+; Turn off no-space-in-time-literal warnings. Default is on.
+; Show_Warning4 = 0
+
+; Turn off multiple-drivers-on-unresolved-signal warnings. Default is on.
+; Show_Warning5 = 0
+
+; Turn off optimization for IEEE std_logic_1164 package. Default is on.
+; Optimize_1164 = 0
+
+; Turn on resolving of ambiguous function overloading in favor of the
+; "explicit" function declaration (not the one automatically created by
+; the compiler for each type declaration). Default is off.
+; The .ini file has Explicit enabled so that std_logic_signed/unsigned
+; will match the behavior of synthesis tools.
+Explicit = 1
+
+; Turn off acceleration of the VITAL packages. Default is to accelerate.
+; NoVital = 1
+
+; Turn off VITAL compliance checking. Default is checking on.
+; NoVitalCheck = 1
+
+; Ignore VITAL compliance checking errors. Default is to not ignore.
+; IgnoreVitalErrors = 1
+
+; Turn off VITAL compliance checking warnings. Default is to show warnings.
+; Show_VitalChecksWarnings = 0
+
+; Keep silent about case statement static warnings.
+; Default is to give a warning.
+; NoCaseStaticError = 1
+
+; Keep silent about warnings caused by aggregates that are not locally static.
+; Default is to give a warning.
+; NoOthersStaticError = 1
+
+; Turn off inclusion of debugging info within design units.
+; Default is to include debugging info.
+; NoDebug = 1
+
+; Turn off "Loading..." messages. Default is messages on.
+; Quiet = 1
+
+; Turn on some limited synthesis rule compliance checking. Checks only:
+;    -- signals used (read) by a process must be in the sensitivity list
+; CheckSynthesis = 1
+
+; Activate optimizations on expressions that do not involve signals,
+; waits, or function/procedure/task invocations. Default is off.
+; ScalarOpts = 1
+
+; Require the user to specify a configuration for all bindings,
+; and do not generate a compile time default binding for the
+; component. This will result in an elaboration error of
+; 'component not bound' if the user fails to do so. Avoids the rare
+; issue of a false dependency upon the unused default binding.
+; RequireConfigForAllDefaultBinding = 1
+
+; Inhibit range checking on subscripts of arrays. Range checking on
+; scalars defined with subtypes is inhibited by default.
+; NoIndexCheck = 1
+
+; Inhibit range checks on all (implicit and explicit) assignments to
+; scalar objects defined with subtypes.
+; NoRangeCheck = 1
+
+[vlog]
+
+; Turn off inclusion of debugging info within design units.
+; Default is to include debugging info.
+; NoDebug = 1
+
+; Turn off "loading..." messages. Default is messages on.
+; Quiet = 1
+
+; Turn on Verilog hazard checking (order-dependent accessing of global vars).
+; Default is off.
+; Hazard = 1
+
+; Turn on converting regular Verilog identifiers to uppercase. Allows case
+; insensitivity for module names. Default is no conversion.
+; UpCase = 1
+
+; Turn on incremental compilation of modules. Default is off.
+; Incremental = 1
+
+; Turns on lint-style checking.
+; Show_Lint = 1
+
+[vsim]
+; Simulator resolution
+; Set to fs, ps, ns, us, ms, or sec with optional prefix of 1, 10, or 100.
+Resolution = ps
+
+; User time unit for run commands
+; Set to default, fs, ps, ns, us, ms, or sec. The default is to use the
+; unit specified for Resolution. For example, if Resolution is 100ps,
+; then UserTimeUnit defaults to ps.
+; Should generally be set to default.
+UserTimeUnit = default
+
+; Default run length
+RunLength = 100 ps
+
+; Maximum iterations that can be run without advancing simulation time
+IterationLimit = 5000
+
+; Directive to license manager:
+; vhdl          Immediately reserve a VHDL license
+; vlog          Immediately reserve a Verilog license
+; plus          Immediately reserve a VHDL and Verilog license
+; nomgc         Do not look for Mentor Graphics Licenses
+; nomti         Do not look for Model Technology Licenses
+; noqueue       Do not wait in the license queue when a license isn't available
+; viewsim	Try for viewer license but accept simulator license(s) instead
+;		of queuing for viewer license
+; License = plus
+
+; Stop the simulator after a VHDL/Verilog assertion message
+; 0 = Note  1 = Warning  2 = Error  3 = Failure  4 = Fatal
+BreakOnAssertion = 3
+
+; Assertion Message Format
+; %S - Severity Level 
+; %R - Report Message
+; %T - Time of assertion
+; %D - Delta
+; %I - Instance or Region pathname (if available)
+; %% - print '%' character
+; AssertionFormat = "** %S: %R\n   Time: %T  Iteration: %D%I\n"
+
+; Assertion File - alternate file for storing VHDL/Verilog assertion messages
+; AssertFile = assert.log
+
+; Default radix for all windows and commands...
+; Set to symbolic, ascii, binary, octal, decimal, hex, unsigned
+DefaultRadix = symbolic
+
+; VSIM Startup command
+; Startup = do startup.do
+
+; File for saving command transcript
+TranscriptFile = transcript
+
+; File for saving command history
+; CommandHistory = cmdhist.log
+
+; Specify whether paths in simulator commands should be described
+; in VHDL or Verilog format.
+; For VHDL, PathSeparator = /
+; For Verilog, PathSeparator = .
+; Must not be the same character as DatasetSeparator.
+PathSeparator = /
+
+; Specify the dataset separator for fully rooted contexts.
+; The default is ':'. For example, sim:/top
+; Must not be the same character as PathSeparator.
+DatasetSeparator = :
+
+; Disable VHDL assertion messages
+; IgnoreNote = 1
+; IgnoreWarning = 1
+; IgnoreError = 1
+; IgnoreFailure = 1
+
+; Default force kind. May be freeze, drive, deposit, or default
+; or in other terms, fixed, wired, or charged.
+; A value of "default" will use the signal kind to determine the
+; force kind, drive for resolved signals, freeze for unresolved signals
+; DefaultForceKind = freeze
+
+; If zero, open files when elaborated; otherwise, open files on
+; first read or write.  Default is 0.
+; DelayFileOpen = 1
+
+; Control VHDL files opened for write.
+;   0 = Buffered, 1 = Unbuffered
+UnbufferedOutput = 0
+
+; Control the number of VHDL files open concurrently.
+; This number should always be less than the current ulimit
+; setting for max file descriptors.
+;   0 = unlimited
+ConcurrentFileLimit = 40
+
+; Control the number of hierarchical regions displayed as
+; part of a signal name shown in the Wave window.
+; A value of zero tells VSIM to display the full name.
+; The default is 0.
+; WaveSignalNameWidth = 0
+
+; Turn off warnings from the std_logic_arith, std_logic_unsigned
+; and std_logic_signed packages.
+; StdArithNoWarnings = 1
+
+; Turn off warnings from the IEEE numeric_std and numeric_bit packages.
+; NumericStdNoWarnings = 1
+
+; Control the format of the (VHDL) FOR generate statement label
+; for each iteration.  Do not quote it.
+; The format string here must contain the conversion codes %s and %d,
+; in that order, and no other conversion codes.  The %s represents
+; the generate_label; the %d represents the generate parameter value
+; at a particular generate iteration (this is the position number if
+; the generate parameter is of an enumeration type).  Embedded whitespace
+; is allowed (but discouraged); leading and trailing whitespace is ignored.
+; Application of the format must result in a unique scope name over all
+; such names in the design so that name lookup can function properly.
+; GenerateFormat = %s__%d
+
+; Specify whether checkpoint files should be compressed.
+; The default is 1 (compressed).
+; CheckpointCompressMode = 0
+
+; List of dynamically loaded objects for Verilog PLI applications
+; Veriuser = veriuser.sl
+
+; Specify default options for the restart command. Options can be one
+; or more of: -force -nobreakpoint -nolist -nolog -nowave
+; DefaultRestartOptions = -force
+
+; HP-UX 10.20 ONLY - Enable memory locking to speed up large designs
+; (> 500 megabyte memory footprint). Default is disabled.
+; Specify number of megabytes to lock.
+; LockedMemory = 1000
+
+; Turn on (1) or off (0) WLF file compression.
+; The default is 1 (compress WLF file).
+; WLFCompress = 0
+
+; Specify whether to save all design hierarchy (1) in the WLF file
+; or only regions containing logged signals (0).
+; The default is 0 (save only regions with logged signals).
+; WLFSaveAllRegions = 1
+
+; WLF file time limit.  Limit WLF file by time, as closely as possible,
+; to the specified amount of simulation time.  When the limit is exceeded
+; the earliest times get truncated from the file.
+; If both time and size limits are specified the most restrictive is used.
+; UserTimeUnits are used if time units are not specified.
+; The default is 0 (no limit).  Example: WLFTimeLimit = {100 ms}
+; WLFTimeLimit = 0
+
+; WLF file size limit.  Limit WLF file size, as closely as possible,
+; to the specified number of megabytes.  If both time and size limits
+; are specified then the most restrictive is used.
+; The default is 0 (no limit).
+; WLFSizeLimit = 1000
+
+; Specify whether or not a WLF file should be deleted when the
+; simulation ends.  A value of 1 will cause the WLF file to be deleted.
+; The default is 0 (do not delete WLF file when simulation ends).
+; WLFDeleteOnQuit = 1
+
+; Automatic SDF compilation
+; Disables automatic compilation of SDF files in flows that support it.
+; Default is on, uncomment to turn off.
+; NoAutoSDFCompile = 1
+
+[lmc]
+
+[msg_system]
+; Change a message severity or suppress a message.
+; The format is: <msg directive> = <msg number>[,<msg number>...]
+; Examples:
+;   note = 3009
+;   warning = 3033
+;   error = 3010,3016
+;   fatal = 3016,3033
+;   suppress = 3009,3016,3043
+; The command verror <msg number> can be used to get the complete
+; description of a message.
+
+; Control transcripting of elaboration/runtime messages.
+; The default is to have messages appear in the transcript and 
+; recorded in the wlf file (messages that are recorded in the
+; wlf file can be viewed in the MsgViewer).  The other settings
+; are to send messages only to the transcript or only to the 
+; wlf file.  The valid values are
+;    both  {default}
+;    tran  {transcript only}
+;    wlf   {wlf file only}
+; msgmode = both
+[Project]
+** Warning: ; Warning -- Do not edit the project properties directly.
+;            Property names are dynamic in nature and property
+;            values have special syntax.  Changing property data directly
+;            can result in a corrupt MPF file.  All project properties
+;            can be modified through project window dialogs.
+Project_Version = 6
+Project_DefaultLib = work
+Project_SortMethod = unused
+Project_Files_Count = 2
+Project_File_0 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/seven_seg.sv
+Project_File_P_0 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1789355084 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 vlog_showsource 0 vlog_hazard 0 cover_optlevel 3 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 0 cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_1 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/seven_seg_tb.sv
+Project_File_P_1 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1788418794 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 vlog_showsource 0 vlog_hazard 0 cover_optlevel 3 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 1 cover_expr 0 dont_compile 0 cover_stmt 0
+Project_Sim_Count = 0
+Project_Folder_Count = 0
+Echo_Compile_Output = 0
+Save_Compile_Report = 1
+Project_Opt_Count = 0
+ForceSoftPaths = 0
+ProjectStatusDelay = 5000
+VERILOG_DoubleClick = Edit
+VERILOG_CustomDoubleClick = 
+SYSTEMVERILOG_DoubleClick = Edit
+SYSTEMVERILOG_CustomDoubleClick = 
+VHDL_DoubleClick = Edit
+VHDL_CustomDoubleClick = 
+PSL_DoubleClick = Edit
+PSL_CustomDoubleClick = 
+TEXT_DoubleClick = Edit
+TEXT_CustomDoubleClick = 
+SYSTEMC_DoubleClick = Edit
+SYSTEMC_CustomDoubleClick = 
+TCL_DoubleClick = Edit
+TCL_CustomDoubleClick = 
+MACRO_DoubleClick = Edit
+MACRO_CustomDoubleClick = 
+VCD_DoubleClick = Edit
+VCD_CustomDoubleClick = 
+SDF_DoubleClick = Edit
+SDF_CustomDoubleClick = 
+XML_DoubleClick = Edit
+XML_CustomDoubleClick = 
+LOGFILE_DoubleClick = Edit
+LOGFILE_CustomDoubleClick = 
+UCDB_DoubleClick = Edit
+UCDB_CustomDoubleClick = 
+TDB_DoubleClick = Edit
+TDB_CustomDoubleClick = 
+UPF_DoubleClick = Edit
+UPF_CustomDoubleClick = 
+PCF_DoubleClick = Edit
+PCF_CustomDoubleClick = 
+PROJECT_DoubleClick = Edit
+PROJECT_CustomDoubleClick = 
+VRM_DoubleClick = Edit
+VRM_CustomDoubleClick = 
+DEBUGDATABASE_DoubleClick = Edit
+DEBUGDATABASE_CustomDoubleClick = 
+DEBUGARCHIVE_DoubleClick = Edit
+DEBUGARCHIVE_CustomDoubleClick = 
+Project_Major_Version = 2020
+Project_Minor_Version = 1

ModelSim/Assignment_1_Q2.cr.mti

@@ -1 +1,16 @@
+/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/lu.sv {1 {vlog -work work -sv -stats=none /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/lu.sv
+Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
+-- Compiling module lu
 
+Top level modules:
+	lu
+
+} {} {}} /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/lu_tb.sv {1 {vlog -work work -sv -stats=none /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/lu_tb.sv
+Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
+-- Compiling module lu
+-- Compiling module lu_tb
+
+Top level modules:
+	lu_tb
+
+} {} {}}

ModelSim/Assignment_1_Q2.mpf

@@ -220,7 +220,7 @@ Resolution = ps
 UserTimeUnit = default
 
 ; Default run length
-RunLength = 100 ps
+RunLength = 0 ps
 
 ; Maximum iterations that can be run without advancing simulation time
 IterationLimit = 5000
@@ -412,9 +412,9 @@ Project_DefaultLib = work
 Project_SortMethod = unused
 Project_Files_Count = 2
 Project_File_0 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/lu.sv
-Project_File_P_0 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 folder {Top Level} last_compile 1788845636 cover_fsm 0 cover_branch 0 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 vlog_showsource 0 vlog_hazard 0 cover_optlevel 3 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 0 cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_P_0 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 last_compile 1789355084 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 0 dont_compile 0 cover_expr 0 cover_stmt 0
 Project_File_1 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/lu_tb.sv
-Project_File_P_1 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 folder {Top Level} last_compile 1788848626 cover_fsm 0 cover_branch 0 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 vlog_showsource 0 vlog_hazard 0 cover_optlevel 3 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 1 cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_P_1 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 last_compile 1788926090 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 1 dont_compile 0 cover_expr 0 cover_stmt 0
 Project_Sim_Count = 0
 Project_Folder_Count = 0
 Echo_Compile_Output = 0

ModelSim/Assignment_1_Q3.cr.mti

@@ -0,0 +1,16 @@
+/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/asu.sv {1 {vlog -work work -sv -stats=none /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/asu.sv
+Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
+-- Compiling module asu
+
+Top level modules:
+	asu
+
+} {} {}} /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/asu_tb.sv {1 {vlog -work work -sv -stats=none /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/asu_tb.sv
+Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
+-- Compiling module asu
+-- Compiling module asu_tb
+
+Top level modules:
+	asu_tb
+
+} {} {}}

ModelSim/Assignment_1_Q3.mpf

@@ -0,0 +1,466 @@
+; Copyright 1991-2009 Mentor Graphics Corporation
+;
+; All Rights Reserved.
+;
+; THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH IS THE PROPERTY OF 
+; MENTOR GRAPHICS CORPORATION OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS.
+;   
+
+[Library]
+std = $MODEL_TECH/../std
+ieee = $MODEL_TECH/../ieee
+verilog = $MODEL_TECH/../verilog
+vital2000 = $MODEL_TECH/../vital2000
+std_developerskit = $MODEL_TECH/../std_developerskit
+synopsys = $MODEL_TECH/../synopsys
+modelsim_lib = $MODEL_TECH/../modelsim_lib
+sv_std = $MODEL_TECH/../sv_std
+
+; Altera Primitive libraries
+;
+; VHDL Section
+;
+altera_mf = $MODEL_TECH/../altera/vhdl/altera_mf
+altera = $MODEL_TECH/../altera/vhdl/altera
+altera_lnsim = $MODEL_TECH/../altera/vhdl/altera_lnsim
+lpm = $MODEL_TECH/../altera/vhdl/220model
+220model = $MODEL_TECH/../altera/vhdl/220model
+maxii = $MODEL_TECH/../altera/vhdl/maxii
+maxv = $MODEL_TECH/../altera/vhdl/maxv
+fiftyfivenm = $MODEL_TECH/../altera/vhdl/fiftyfivenm
+sgate = $MODEL_TECH/../altera/vhdl/sgate
+arriaii = $MODEL_TECH/../altera/vhdl/arriaii
+arriaii_hssi = $MODEL_TECH/../altera/vhdl/arriaii_hssi
+arriaii_pcie_hip = $MODEL_TECH/../altera/vhdl/arriaii_pcie_hip
+arriaiigz = $MODEL_TECH/../altera/vhdl/arriaiigz
+arriaiigz_hssi = $MODEL_TECH/../altera/vhdl/arriaiigz_hssi
+arriaiigz_pcie_hip = $MODEL_TECH/../altera/vhdl/arriaiigz_pcie_hip
+stratixiv = $MODEL_TECH/../altera/vhdl/stratixiv
+stratixiv_hssi = $MODEL_TECH/../altera/vhdl/stratixiv_hssi
+stratixiv_pcie_hip = $MODEL_TECH/../altera/vhdl/stratixiv_pcie_hip
+cycloneiv = $MODEL_TECH/../altera/vhdl/cycloneiv
+cycloneiv_hssi = $MODEL_TECH/../altera/vhdl/cycloneiv_hssi
+cycloneiv_pcie_hip = $MODEL_TECH/../altera/vhdl/cycloneiv_pcie_hip
+cycloneive = $MODEL_TECH/../altera/vhdl/cycloneive
+stratixv = $MODEL_TECH/../altera/vhdl/stratixv
+stratixv_hssi = $MODEL_TECH/../altera/vhdl/stratixv_hssi
+stratixv_pcie_hip = $MODEL_TECH/../altera/vhdl/stratixv_pcie_hip
+arriavgz = $MODEL_TECH/../altera/vhdl/arriavgz
+arriavgz_hssi = $MODEL_TECH/../altera/vhdl/arriavgz_hssi
+arriavgz_pcie_hip = $MODEL_TECH/../altera/vhdl/arriavgz_pcie_hip
+arriav = $MODEL_TECH/../altera/vhdl/arriav
+cyclonev = $MODEL_TECH/../altera/vhdl/cyclonev
+twentynm = $MODEL_TECH/../altera/vhdl/twentynm
+twentynm_hssi = $MODEL_TECH/../altera/vhdl/twentynm_hssi
+twentynm_hip = $MODEL_TECH/../altera/vhdl/twentynm_hip
+cyclone10lp = $MODEL_TECH/../altera/vhdl/cyclone10lp
+;
+; Verilog Section
+;
+altera_mf_ver = $MODEL_TECH/../altera/verilog/altera_mf
+altera_ver = $MODEL_TECH/../altera/verilog/altera
+altera_lnsim_ver = $MODEL_TECH/../altera/verilog/altera_lnsim
+lpm_ver = $MODEL_TECH/../altera/verilog/220model
+220model_ver = $MODEL_TECH/../altera/verilog/220model
+maxii_ver = $MODEL_TECH/../altera/verilog/maxii
+maxv_ver = $MODEL_TECH/../altera/verilog/maxv
+fiftyfivenm_ver = $MODEL_TECH/../altera/verilog/fiftyfivenm
+sgate_ver = $MODEL_TECH/../altera/verilog/sgate
+arriaii_ver = $MODEL_TECH/../altera/verilog/arriaii
+arriaii_hssi_ver = $MODEL_TECH/../altera/verilog/arriaii_hssi
+arriaii_pcie_hip_ver = $MODEL_TECH/../altera/verilog/arriaii_pcie_hip
+arriaiigz_ver = $MODEL_TECH/../altera/verilog/arriaiigz
+arriaiigz_hssi_ver = $MODEL_TECH/../altera/verilog/arriaiigz_hssi
+arriaiigz_pcie_hip_ver = $MODEL_TECH/../altera/verilog/arriaiigz_pcie_hip
+stratixiv_ver = $MODEL_TECH/../altera/verilog/stratixiv
+stratixiv_hssi_ver = $MODEL_TECH/../altera/verilog/stratixiv_hssi
+stratixiv_pcie_hip_ver = $MODEL_TECH/../altera/verilog/stratixiv_pcie_hip
+stratixv_ver = $MODEL_TECH/../altera/verilog/stratixv
+stratixv_hssi_ver = $MODEL_TECH/../altera/verilog/stratixv_hssi
+stratixv_pcie_hip_ver = $MODEL_TECH/../altera/verilog/stratixv_pcie_hip
+arriavgz_ver = $MODEL_TECH/../altera/verilog/arriavgz
+arriavgz_hssi_ver = $MODEL_TECH/../altera/verilog/arriavgz_hssi
+arriavgz_pcie_hip_ver = $MODEL_TECH/../altera/verilog/arriavgz_pcie_hip
+arriav_ver = $MODEL_TECH/../altera/verilog/arriav
+arriav_hssi_ver = $MODEL_TECH/../altera/verilog/arriav_hssi
+arriav_pcie_hip_ver = $MODEL_TECH/../altera/verilog/arriav_pcie_hip
+cyclonev_ver = $MODEL_TECH/../altera/verilog/cyclonev
+cyclonev_hssi_ver = $MODEL_TECH/../altera/verilog/cyclonev_hssi
+cyclonev_pcie_hip_ver = $MODEL_TECH/../altera/verilog/cyclonev_pcie_hip
+cycloneiv_ver = $MODEL_TECH/../altera/verilog/cycloneiv
+cycloneiv_hssi_ver = $MODEL_TECH/../altera/verilog/cycloneiv_hssi
+cycloneiv_pcie_hip_ver = $MODEL_TECH/../altera/verilog/cycloneiv_pcie_hip
+cycloneive_ver = $MODEL_TECH/../altera/verilog/cycloneive
+twentynm_ver = $MODEL_TECH/../altera/verilog/twentynm
+twentynm_hssi_ver = $MODEL_TECH/../altera/verilog/twentynm_hssi
+twentynm_hip_ver = $MODEL_TECH/../altera/verilog/twentynm_hip
+cyclone10lp_ver = $MODEL_TECH/../altera/verilog/cyclone10lp
+
+work = work
+[vcom]
+; VHDL93 variable selects language version as the default. 
+; Default is VHDL-2002.
+; Value of 0 or 1987 for VHDL-1987.
+; Value of 1 or 1993 for VHDL-1993.
+; Default or value of 2 or 2002 for VHDL-2002.
+; Default or value of 3 or 2008 for VHDL-2008.
+VHDL93 = 2002
+
+; Show source line containing error. Default is off.
+; Show_source = 1
+
+; Turn off unbound-component warnings. Default is on.
+; Show_Warning1 = 0
+
+; Turn off process-without-a-wait-statement warnings. Default is on.
+; Show_Warning2 = 0
+
+; Turn off null-range warnings. Default is on.
+; Show_Warning3 = 0
+
+; Turn off no-space-in-time-literal warnings. Default is on.
+; Show_Warning4 = 0
+
+; Turn off multiple-drivers-on-unresolved-signal warnings. Default is on.
+; Show_Warning5 = 0
+
+; Turn off optimization for IEEE std_logic_1164 package. Default is on.
+; Optimize_1164 = 0
+
+; Turn on resolving of ambiguous function overloading in favor of the
+; "explicit" function declaration (not the one automatically created by
+; the compiler for each type declaration). Default is off.
+; The .ini file has Explicit enabled so that std_logic_signed/unsigned
+; will match the behavior of synthesis tools.
+Explicit = 1
+
+; Turn off acceleration of the VITAL packages. Default is to accelerate.
+; NoVital = 1
+
+; Turn off VITAL compliance checking. Default is checking on.
+; NoVitalCheck = 1
+
+; Ignore VITAL compliance checking errors. Default is to not ignore.
+; IgnoreVitalErrors = 1
+
+; Turn off VITAL compliance checking warnings. Default is to show warnings.
+; Show_VitalChecksWarnings = 0
+
+; Keep silent about case statement static warnings.
+; Default is to give a warning.
+; NoCaseStaticError = 1
+
+; Keep silent about warnings caused by aggregates that are not locally static.
+; Default is to give a warning.
+; NoOthersStaticError = 1
+
+; Turn off inclusion of debugging info within design units.
+; Default is to include debugging info.
+; NoDebug = 1
+
+; Turn off "Loading..." messages. Default is messages on.
+; Quiet = 1
+
+; Turn on some limited synthesis rule compliance checking. Checks only:
+;    -- signals used (read) by a process must be in the sensitivity list
+; CheckSynthesis = 1
+
+; Activate optimizations on expressions that do not involve signals,
+; waits, or function/procedure/task invocations. Default is off.
+; ScalarOpts = 1
+
+; Require the user to specify a configuration for all bindings,
+; and do not generate a compile time default binding for the
+; component. This will result in an elaboration error of
+; 'component not bound' if the user fails to do so. Avoids the rare
+; issue of a false dependency upon the unused default binding.
+; RequireConfigForAllDefaultBinding = 1
+
+; Inhibit range checking on subscripts of arrays. Range checking on
+; scalars defined with subtypes is inhibited by default.
+; NoIndexCheck = 1
+
+; Inhibit range checks on all (implicit and explicit) assignments to
+; scalar objects defined with subtypes.
+; NoRangeCheck = 1
+
+[vlog]
+
+; Turn off inclusion of debugging info within design units.
+; Default is to include debugging info.
+; NoDebug = 1
+
+; Turn off "loading..." messages. Default is messages on.
+; Quiet = 1
+
+; Turn on Verilog hazard checking (order-dependent accessing of global vars).
+; Default is off.
+; Hazard = 1
+
+; Turn on converting regular Verilog identifiers to uppercase. Allows case
+; insensitivity for module names. Default is no conversion.
+; UpCase = 1
+
+; Turn on incremental compilation of modules. Default is off.
+; Incremental = 1
+
+; Turns on lint-style checking.
+; Show_Lint = 1
+
+[vsim]
+; Simulator resolution
+; Set to fs, ps, ns, us, ms, or sec with optional prefix of 1, 10, or 100.
+Resolution = ps
+
+; User time unit for run commands
+; Set to default, fs, ps, ns, us, ms, or sec. The default is to use the
+; unit specified for Resolution. For example, if Resolution is 100ps,
+; then UserTimeUnit defaults to ps.
+; Should generally be set to default.
+UserTimeUnit = default
+
+; Default run length
+RunLength = 100 ps
+
+; Maximum iterations that can be run without advancing simulation time
+IterationLimit = 5000
+
+; Directive to license manager:
+; vhdl          Immediately reserve a VHDL license
+; vlog          Immediately reserve a Verilog license
+; plus          Immediately reserve a VHDL and Verilog license
+; nomgc         Do not look for Mentor Graphics Licenses
+; nomti         Do not look for Model Technology Licenses
+; noqueue       Do not wait in the license queue when a license isn't available
+; viewsim	Try for viewer license but accept simulator license(s) instead
+;		of queuing for viewer license
+; License = plus
+
+; Stop the simulator after a VHDL/Verilog assertion message
+; 0 = Note  1 = Warning  2 = Error  3 = Failure  4 = Fatal
+BreakOnAssertion = 3
+
+; Assertion Message Format
+; %S - Severity Level 
+; %R - Report Message
+; %T - Time of assertion
+; %D - Delta
+; %I - Instance or Region pathname (if available)
+; %% - print '%' character
+; AssertionFormat = "** %S: %R\n   Time: %T  Iteration: %D%I\n"
+
+; Assertion File - alternate file for storing VHDL/Verilog assertion messages
+; AssertFile = assert.log
+
+; Default radix for all windows and commands...
+; Set to symbolic, ascii, binary, octal, decimal, hex, unsigned
+DefaultRadix = symbolic
+
+; VSIM Startup command
+; Startup = do startup.do
+
+; File for saving command transcript
+TranscriptFile = transcript
+
+; File for saving command history
+; CommandHistory = cmdhist.log
+
+; Specify whether paths in simulator commands should be described
+; in VHDL or Verilog format.
+; For VHDL, PathSeparator = /
+; For Verilog, PathSeparator = .
+; Must not be the same character as DatasetSeparator.
+PathSeparator = /
+
+; Specify the dataset separator for fully rooted contexts.
+; The default is ':'. For example, sim:/top
+; Must not be the same character as PathSeparator.
+DatasetSeparator = :
+
+; Disable VHDL assertion messages
+; IgnoreNote = 1
+; IgnoreWarning = 1
+; IgnoreError = 1
+; IgnoreFailure = 1
+
+; Default force kind. May be freeze, drive, deposit, or default
+; or in other terms, fixed, wired, or charged.
+; A value of "default" will use the signal kind to determine the
+; force kind, drive for resolved signals, freeze for unresolved signals
+; DefaultForceKind = freeze
+
+; If zero, open files when elaborated; otherwise, open files on
+; first read or write.  Default is 0.
+; DelayFileOpen = 1
+
+; Control VHDL files opened for write.
+;   0 = Buffered, 1 = Unbuffered
+UnbufferedOutput = 0
+
+; Control the number of VHDL files open concurrently.
+; This number should always be less than the current ulimit
+; setting for max file descriptors.
+;   0 = unlimited
+ConcurrentFileLimit = 40
+
+; Control the number of hierarchical regions displayed as
+; part of a signal name shown in the Wave window.
+; A value of zero tells VSIM to display the full name.
+; The default is 0.
+; WaveSignalNameWidth = 0
+
+; Turn off warnings from the std_logic_arith, std_logic_unsigned
+; and std_logic_signed packages.
+; StdArithNoWarnings = 1
+
+; Turn off warnings from the IEEE numeric_std and numeric_bit packages.
+; NumericStdNoWarnings = 1
+
+; Control the format of the (VHDL) FOR generate statement label
+; for each iteration.  Do not quote it.
+; The format string here must contain the conversion codes %s and %d,
+; in that order, and no other conversion codes.  The %s represents
+; the generate_label; the %d represents the generate parameter value
+; at a particular generate iteration (this is the position number if
+; the generate parameter is of an enumeration type).  Embedded whitespace
+; is allowed (but discouraged); leading and trailing whitespace is ignored.
+; Application of the format must result in a unique scope name over all
+; such names in the design so that name lookup can function properly.
+; GenerateFormat = %s__%d
+
+; Specify whether checkpoint files should be compressed.
+; The default is 1 (compressed).
+; CheckpointCompressMode = 0
+
+; List of dynamically loaded objects for Verilog PLI applications
+; Veriuser = veriuser.sl
+
+; Specify default options for the restart command. Options can be one
+; or more of: -force -nobreakpoint -nolist -nolog -nowave
+; DefaultRestartOptions = -force
+
+; HP-UX 10.20 ONLY - Enable memory locking to speed up large designs
+; (> 500 megabyte memory footprint). Default is disabled.
+; Specify number of megabytes to lock.
+; LockedMemory = 1000
+
+; Turn on (1) or off (0) WLF file compression.
+; The default is 1 (compress WLF file).
+; WLFCompress = 0
+
+; Specify whether to save all design hierarchy (1) in the WLF file
+; or only regions containing logged signals (0).
+; The default is 0 (save only regions with logged signals).
+; WLFSaveAllRegions = 1
+
+; WLF file time limit.  Limit WLF file by time, as closely as possible,
+; to the specified amount of simulation time.  When the limit is exceeded
+; the earliest times get truncated from the file.
+; If both time and size limits are specified the most restrictive is used.
+; UserTimeUnits are used if time units are not specified.
+; The default is 0 (no limit).  Example: WLFTimeLimit = {100 ms}
+; WLFTimeLimit = 0
+
+; WLF file size limit.  Limit WLF file size, as closely as possible,
+; to the specified number of megabytes.  If both time and size limits
+; are specified then the most restrictive is used.
+; The default is 0 (no limit).
+; WLFSizeLimit = 1000
+
+; Specify whether or not a WLF file should be deleted when the
+; simulation ends.  A value of 1 will cause the WLF file to be deleted.
+; The default is 0 (do not delete WLF file when simulation ends).
+; WLFDeleteOnQuit = 1
+
+; Automatic SDF compilation
+; Disables automatic compilation of SDF files in flows that support it.
+; Default is on, uncomment to turn off.
+; NoAutoSDFCompile = 1
+
+[lmc]
+
+[msg_system]
+; Change a message severity or suppress a message.
+; The format is: <msg directive> = <msg number>[,<msg number>...]
+; Examples:
+;   note = 3009
+;   warning = 3033
+;   error = 3010,3016
+;   fatal = 3016,3033
+;   suppress = 3009,3016,3043
+; The command verror <msg number> can be used to get the complete
+; description of a message.
+
+; Control transcripting of elaboration/runtime messages.
+; The default is to have messages appear in the transcript and 
+; recorded in the wlf file (messages that are recorded in the
+; wlf file can be viewed in the MsgViewer).  The other settings
+; are to send messages only to the transcript or only to the 
+; wlf file.  The valid values are
+;    both  {default}
+;    tran  {transcript only}
+;    wlf   {wlf file only}
+; msgmode = both
+[Project]
+** Warning: ; Warning -- Do not edit the project properties directly.
+;            Property names are dynamic in nature and property
+;            values have special syntax.  Changing property data directly
+;            can result in a corrupt MPF file.  All project properties
+;            can be modified through project window dialogs.
+Project_Version = 6
+Project_DefaultLib = work
+Project_SortMethod = unused
+Project_Files_Count = 2
+Project_File_0 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/asu.sv
+Project_File_P_0 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 folder {Top Level} last_compile 1789355084 cover_fsm 0 cover_branch 0 vlog_noload 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 0 dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_1 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/asu_tb.sv
+Project_File_P_1 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 folder {Top Level} last_compile 1788926090 cover_fsm 0 cover_branch 0 vlog_noload 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 1 dont_compile 0 cover_expr 0 cover_stmt 0
+Project_Sim_Count = 0
+Project_Folder_Count = 0
+Echo_Compile_Output = 0
+Save_Compile_Report = 1
+Project_Opt_Count = 0
+ForceSoftPaths = 0
+ProjectStatusDelay = 5000
+VERILOG_DoubleClick = Edit
+VERILOG_CustomDoubleClick = 
+SYSTEMVERILOG_DoubleClick = Edit
+SYSTEMVERILOG_CustomDoubleClick = 
+VHDL_DoubleClick = Edit
+VHDL_CustomDoubleClick = 
+PSL_DoubleClick = Edit
+PSL_CustomDoubleClick = 
+TEXT_DoubleClick = Edit
+TEXT_CustomDoubleClick = 
+SYSTEMC_DoubleClick = Edit
+SYSTEMC_CustomDoubleClick = 
+TCL_DoubleClick = Edit
+TCL_CustomDoubleClick = 
+MACRO_DoubleClick = Edit
+MACRO_CustomDoubleClick = 
+VCD_DoubleClick = Edit
+VCD_CustomDoubleClick = 
+SDF_DoubleClick = Edit
+SDF_CustomDoubleClick = 
+XML_DoubleClick = Edit
+XML_CustomDoubleClick = 
+LOGFILE_DoubleClick = Edit
+LOGFILE_CustomDoubleClick = 
+UCDB_DoubleClick = Edit
+UCDB_CustomDoubleClick = 
+TDB_DoubleClick = Edit
+TDB_CustomDoubleClick = 
+UPF_DoubleClick = Edit
+UPF_CustomDoubleClick = 
+PCF_DoubleClick = Edit
+PCF_CustomDoubleClick = 
+PROJECT_DoubleClick = Edit
+PROJECT_CustomDoubleClick = 
+VRM_DoubleClick = Edit
+VRM_CustomDoubleClick = 
+DEBUGDATABASE_DoubleClick = Edit
+DEBUGDATABASE_CustomDoubleClick = 
+DEBUGARCHIVE_DoubleClick = Edit
+DEBUGARCHIVE_CustomDoubleClick = 
+Project_Major_Version = 2020
+Project_Minor_Version = 1

ModelSim/Assignment_1_Q4.cr.mti

@@ -0,0 +1,20 @@
+/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/alu.sv {1 {vlog -work work -sv -stats=none /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/alu.sv
+Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
+-- Compiling module asu
+-- Compiling module lu
+-- Compiling module alu
+
+Top level modules:
+	alu
+
+} {} {}} /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/alu_tb.sv {1 {vlog -work work -sv -stats=none /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/alu_tb.sv
+Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
+-- Compiling module asu
+-- Compiling module lu
+-- Compiling module alu
+-- Compiling module alu_tb
+
+Top level modules:
+	alu_tb
+
+} {} {}}

ModelSim/Assignment_1_Q4.mpf

@@ -0,0 +1,466 @@
+; Copyright 1991-2009 Mentor Graphics Corporation
+;
+; All Rights Reserved.
+;
+; THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH IS THE PROPERTY OF 
+; MENTOR GRAPHICS CORPORATION OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS.
+;   
+
+[Library]
+std = $MODEL_TECH/../std
+ieee = $MODEL_TECH/../ieee
+verilog = $MODEL_TECH/../verilog
+vital2000 = $MODEL_TECH/../vital2000
+std_developerskit = $MODEL_TECH/../std_developerskit
+synopsys = $MODEL_TECH/../synopsys
+modelsim_lib = $MODEL_TECH/../modelsim_lib
+sv_std = $MODEL_TECH/../sv_std
+
+; Altera Primitive libraries
+;
+; VHDL Section
+;
+altera_mf = $MODEL_TECH/../altera/vhdl/altera_mf
+altera = $MODEL_TECH/../altera/vhdl/altera
+altera_lnsim = $MODEL_TECH/../altera/vhdl/altera_lnsim
+lpm = $MODEL_TECH/../altera/vhdl/220model
+220model = $MODEL_TECH/../altera/vhdl/220model
+maxii = $MODEL_TECH/../altera/vhdl/maxii
+maxv = $MODEL_TECH/../altera/vhdl/maxv
+fiftyfivenm = $MODEL_TECH/../altera/vhdl/fiftyfivenm
+sgate = $MODEL_TECH/../altera/vhdl/sgate
+arriaii = $MODEL_TECH/../altera/vhdl/arriaii
+arriaii_hssi = $MODEL_TECH/../altera/vhdl/arriaii_hssi
+arriaii_pcie_hip = $MODEL_TECH/../altera/vhdl/arriaii_pcie_hip
+arriaiigz = $MODEL_TECH/../altera/vhdl/arriaiigz
+arriaiigz_hssi = $MODEL_TECH/../altera/vhdl/arriaiigz_hssi
+arriaiigz_pcie_hip = $MODEL_TECH/../altera/vhdl/arriaiigz_pcie_hip
+stratixiv = $MODEL_TECH/../altera/vhdl/stratixiv
+stratixiv_hssi = $MODEL_TECH/../altera/vhdl/stratixiv_hssi
+stratixiv_pcie_hip = $MODEL_TECH/../altera/vhdl/stratixiv_pcie_hip
+cycloneiv = $MODEL_TECH/../altera/vhdl/cycloneiv
+cycloneiv_hssi = $MODEL_TECH/../altera/vhdl/cycloneiv_hssi
+cycloneiv_pcie_hip = $MODEL_TECH/../altera/vhdl/cycloneiv_pcie_hip
+cycloneive = $MODEL_TECH/../altera/vhdl/cycloneive
+stratixv = $MODEL_TECH/../altera/vhdl/stratixv
+stratixv_hssi = $MODEL_TECH/../altera/vhdl/stratixv_hssi
+stratixv_pcie_hip = $MODEL_TECH/../altera/vhdl/stratixv_pcie_hip
+arriavgz = $MODEL_TECH/../altera/vhdl/arriavgz
+arriavgz_hssi = $MODEL_TECH/../altera/vhdl/arriavgz_hssi
+arriavgz_pcie_hip = $MODEL_TECH/../altera/vhdl/arriavgz_pcie_hip
+arriav = $MODEL_TECH/../altera/vhdl/arriav
+cyclonev = $MODEL_TECH/../altera/vhdl/cyclonev
+twentynm = $MODEL_TECH/../altera/vhdl/twentynm
+twentynm_hssi = $MODEL_TECH/../altera/vhdl/twentynm_hssi
+twentynm_hip = $MODEL_TECH/../altera/vhdl/twentynm_hip
+cyclone10lp = $MODEL_TECH/../altera/vhdl/cyclone10lp
+;
+; Verilog Section
+;
+altera_mf_ver = $MODEL_TECH/../altera/verilog/altera_mf
+altera_ver = $MODEL_TECH/../altera/verilog/altera
+altera_lnsim_ver = $MODEL_TECH/../altera/verilog/altera_lnsim
+lpm_ver = $MODEL_TECH/../altera/verilog/220model
+220model_ver = $MODEL_TECH/../altera/verilog/220model
+maxii_ver = $MODEL_TECH/../altera/verilog/maxii
+maxv_ver = $MODEL_TECH/../altera/verilog/maxv
+fiftyfivenm_ver = $MODEL_TECH/../altera/verilog/fiftyfivenm
+sgate_ver = $MODEL_TECH/../altera/verilog/sgate
+arriaii_ver = $MODEL_TECH/../altera/verilog/arriaii
+arriaii_hssi_ver = $MODEL_TECH/../altera/verilog/arriaii_hssi
+arriaii_pcie_hip_ver = $MODEL_TECH/../altera/verilog/arriaii_pcie_hip
+arriaiigz_ver = $MODEL_TECH/../altera/verilog/arriaiigz
+arriaiigz_hssi_ver = $MODEL_TECH/../altera/verilog/arriaiigz_hssi
+arriaiigz_pcie_hip_ver = $MODEL_TECH/../altera/verilog/arriaiigz_pcie_hip
+stratixiv_ver = $MODEL_TECH/../altera/verilog/stratixiv
+stratixiv_hssi_ver = $MODEL_TECH/../altera/verilog/stratixiv_hssi
+stratixiv_pcie_hip_ver = $MODEL_TECH/../altera/verilog/stratixiv_pcie_hip
+stratixv_ver = $MODEL_TECH/../altera/verilog/stratixv
+stratixv_hssi_ver = $MODEL_TECH/../altera/verilog/stratixv_hssi
+stratixv_pcie_hip_ver = $MODEL_TECH/../altera/verilog/stratixv_pcie_hip
+arriavgz_ver = $MODEL_TECH/../altera/verilog/arriavgz
+arriavgz_hssi_ver = $MODEL_TECH/../altera/verilog/arriavgz_hssi
+arriavgz_pcie_hip_ver = $MODEL_TECH/../altera/verilog/arriavgz_pcie_hip
+arriav_ver = $MODEL_TECH/../altera/verilog/arriav
+arriav_hssi_ver = $MODEL_TECH/../altera/verilog/arriav_hssi
+arriav_pcie_hip_ver = $MODEL_TECH/../altera/verilog/arriav_pcie_hip
+cyclonev_ver = $MODEL_TECH/../altera/verilog/cyclonev
+cyclonev_hssi_ver = $MODEL_TECH/../altera/verilog/cyclonev_hssi
+cyclonev_pcie_hip_ver = $MODEL_TECH/../altera/verilog/cyclonev_pcie_hip
+cycloneiv_ver = $MODEL_TECH/../altera/verilog/cycloneiv
+cycloneiv_hssi_ver = $MODEL_TECH/../altera/verilog/cycloneiv_hssi
+cycloneiv_pcie_hip_ver = $MODEL_TECH/../altera/verilog/cycloneiv_pcie_hip
+cycloneive_ver = $MODEL_TECH/../altera/verilog/cycloneive
+twentynm_ver = $MODEL_TECH/../altera/verilog/twentynm
+twentynm_hssi_ver = $MODEL_TECH/../altera/verilog/twentynm_hssi
+twentynm_hip_ver = $MODEL_TECH/../altera/verilog/twentynm_hip
+cyclone10lp_ver = $MODEL_TECH/../altera/verilog/cyclone10lp
+
+work = work
+[vcom]
+; VHDL93 variable selects language version as the default. 
+; Default is VHDL-2002.
+; Value of 0 or 1987 for VHDL-1987.
+; Value of 1 or 1993 for VHDL-1993.
+; Default or value of 2 or 2002 for VHDL-2002.
+; Default or value of 3 or 2008 for VHDL-2008.
+VHDL93 = 2002
+
+; Show source line containing error. Default is off.
+; Show_source = 1
+
+; Turn off unbound-component warnings. Default is on.
+; Show_Warning1 = 0
+
+; Turn off process-without-a-wait-statement warnings. Default is on.
+; Show_Warning2 = 0
+
+; Turn off null-range warnings. Default is on.
+; Show_Warning3 = 0
+
+; Turn off no-space-in-time-literal warnings. Default is on.
+; Show_Warning4 = 0
+
+; Turn off multiple-drivers-on-unresolved-signal warnings. Default is on.
+; Show_Warning5 = 0
+
+; Turn off optimization for IEEE std_logic_1164 package. Default is on.
+; Optimize_1164 = 0
+
+; Turn on resolving of ambiguous function overloading in favor of the
+; "explicit" function declaration (not the one automatically created by
+; the compiler for each type declaration). Default is off.
+; The .ini file has Explicit enabled so that std_logic_signed/unsigned
+; will match the behavior of synthesis tools.
+Explicit = 1
+
+; Turn off acceleration of the VITAL packages. Default is to accelerate.
+; NoVital = 1
+
+; Turn off VITAL compliance checking. Default is checking on.
+; NoVitalCheck = 1
+
+; Ignore VITAL compliance checking errors. Default is to not ignore.
+; IgnoreVitalErrors = 1
+
+; Turn off VITAL compliance checking warnings. Default is to show warnings.
+; Show_VitalChecksWarnings = 0
+
+; Keep silent about case statement static warnings.
+; Default is to give a warning.
+; NoCaseStaticError = 1
+
+; Keep silent about warnings caused by aggregates that are not locally static.
+; Default is to give a warning.
+; NoOthersStaticError = 1
+
+; Turn off inclusion of debugging info within design units.
+; Default is to include debugging info.
+; NoDebug = 1
+
+; Turn off "Loading..." messages. Default is messages on.
+; Quiet = 1
+
+; Turn on some limited synthesis rule compliance checking. Checks only:
+;    -- signals used (read) by a process must be in the sensitivity list
+; CheckSynthesis = 1
+
+; Activate optimizations on expressions that do not involve signals,
+; waits, or function/procedure/task invocations. Default is off.
+; ScalarOpts = 1
+
+; Require the user to specify a configuration for all bindings,
+; and do not generate a compile time default binding for the
+; component. This will result in an elaboration error of
+; 'component not bound' if the user fails to do so. Avoids the rare
+; issue of a false dependency upon the unused default binding.
+; RequireConfigForAllDefaultBinding = 1
+
+; Inhibit range checking on subscripts of arrays. Range checking on
+; scalars defined with subtypes is inhibited by default.
+; NoIndexCheck = 1
+
+; Inhibit range checks on all (implicit and explicit) assignments to
+; scalar objects defined with subtypes.
+; NoRangeCheck = 1
+
+[vlog]
+
+; Turn off inclusion of debugging info within design units.
+; Default is to include debugging info.
+; NoDebug = 1
+
+; Turn off "loading..." messages. Default is messages on.
+; Quiet = 1
+
+; Turn on Verilog hazard checking (order-dependent accessing of global vars).
+; Default is off.
+; Hazard = 1
+
+; Turn on converting regular Verilog identifiers to uppercase. Allows case
+; insensitivity for module names. Default is no conversion.
+; UpCase = 1
+
+; Turn on incremental compilation of modules. Default is off.
+; Incremental = 1
+
+; Turns on lint-style checking.
+; Show_Lint = 1
+
+[vsim]
+; Simulator resolution
+; Set to fs, ps, ns, us, ms, or sec with optional prefix of 1, 10, or 100.
+Resolution = ps
+
+; User time unit for run commands
+; Set to default, fs, ps, ns, us, ms, or sec. The default is to use the
+; unit specified for Resolution. For example, if Resolution is 100ps,
+; then UserTimeUnit defaults to ps.
+; Should generally be set to default.
+UserTimeUnit = default
+
+; Default run length
+RunLength = 100 ps
+
+; Maximum iterations that can be run without advancing simulation time
+IterationLimit = 5000
+
+; Directive to license manager:
+; vhdl          Immediately reserve a VHDL license
+; vlog          Immediately reserve a Verilog license
+; plus          Immediately reserve a VHDL and Verilog license
+; nomgc         Do not look for Mentor Graphics Licenses
+; nomti         Do not look for Model Technology Licenses
+; noqueue       Do not wait in the license queue when a license isn't available
+; viewsim	Try for viewer license but accept simulator license(s) instead
+;		of queuing for viewer license
+; License = plus
+
+; Stop the simulator after a VHDL/Verilog assertion message
+; 0 = Note  1 = Warning  2 = Error  3 = Failure  4 = Fatal
+BreakOnAssertion = 3
+
+; Assertion Message Format
+; %S - Severity Level 
+; %R - Report Message
+; %T - Time of assertion
+; %D - Delta
+; %I - Instance or Region pathname (if available)
+; %% - print '%' character
+; AssertionFormat = "** %S: %R\n   Time: %T  Iteration: %D%I\n"
+
+; Assertion File - alternate file for storing VHDL/Verilog assertion messages
+; AssertFile = assert.log
+
+; Default radix for all windows and commands...
+; Set to symbolic, ascii, binary, octal, decimal, hex, unsigned
+DefaultRadix = symbolic
+
+; VSIM Startup command
+; Startup = do startup.do
+
+; File for saving command transcript
+TranscriptFile = transcript
+
+; File for saving command history
+; CommandHistory = cmdhist.log
+
+; Specify whether paths in simulator commands should be described
+; in VHDL or Verilog format.
+; For VHDL, PathSeparator = /
+; For Verilog, PathSeparator = .
+; Must not be the same character as DatasetSeparator.
+PathSeparator = /
+
+; Specify the dataset separator for fully rooted contexts.
+; The default is ':'. For example, sim:/top
+; Must not be the same character as PathSeparator.
+DatasetSeparator = :
+
+; Disable VHDL assertion messages
+; IgnoreNote = 1
+; IgnoreWarning = 1
+; IgnoreError = 1
+; IgnoreFailure = 1
+
+; Default force kind. May be freeze, drive, deposit, or default
+; or in other terms, fixed, wired, or charged.
+; A value of "default" will use the signal kind to determine the
+; force kind, drive for resolved signals, freeze for unresolved signals
+; DefaultForceKind = freeze
+
+; If zero, open files when elaborated; otherwise, open files on
+; first read or write.  Default is 0.
+; DelayFileOpen = 1
+
+; Control VHDL files opened for write.
+;   0 = Buffered, 1 = Unbuffered
+UnbufferedOutput = 0
+
+; Control the number of VHDL files open concurrently.
+; This number should always be less than the current ulimit
+; setting for max file descriptors.
+;   0 = unlimited
+ConcurrentFileLimit = 40
+
+; Control the number of hierarchical regions displayed as
+; part of a signal name shown in the Wave window.
+; A value of zero tells VSIM to display the full name.
+; The default is 0.
+; WaveSignalNameWidth = 0
+
+; Turn off warnings from the std_logic_arith, std_logic_unsigned
+; and std_logic_signed packages.
+; StdArithNoWarnings = 1
+
+; Turn off warnings from the IEEE numeric_std and numeric_bit packages.
+; NumericStdNoWarnings = 1
+
+; Control the format of the (VHDL) FOR generate statement label
+; for each iteration.  Do not quote it.
+; The format string here must contain the conversion codes %s and %d,
+; in that order, and no other conversion codes.  The %s represents
+; the generate_label; the %d represents the generate parameter value
+; at a particular generate iteration (this is the position number if
+; the generate parameter is of an enumeration type).  Embedded whitespace
+; is allowed (but discouraged); leading and trailing whitespace is ignored.
+; Application of the format must result in a unique scope name over all
+; such names in the design so that name lookup can function properly.
+; GenerateFormat = %s__%d
+
+; Specify whether checkpoint files should be compressed.
+; The default is 1 (compressed).
+; CheckpointCompressMode = 0
+
+; List of dynamically loaded objects for Verilog PLI applications
+; Veriuser = veriuser.sl
+
+; Specify default options for the restart command. Options can be one
+; or more of: -force -nobreakpoint -nolist -nolog -nowave
+; DefaultRestartOptions = -force
+
+; HP-UX 10.20 ONLY - Enable memory locking to speed up large designs
+; (> 500 megabyte memory footprint). Default is disabled.
+; Specify number of megabytes to lock.
+; LockedMemory = 1000
+
+; Turn on (1) or off (0) WLF file compression.
+; The default is 1 (compress WLF file).
+; WLFCompress = 0
+
+; Specify whether to save all design hierarchy (1) in the WLF file
+; or only regions containing logged signals (0).
+; The default is 0 (save only regions with logged signals).
+; WLFSaveAllRegions = 1
+
+; WLF file time limit.  Limit WLF file by time, as closely as possible,
+; to the specified amount of simulation time.  When the limit is exceeded
+; the earliest times get truncated from the file.
+; If both time and size limits are specified the most restrictive is used.
+; UserTimeUnits are used if time units are not specified.
+; The default is 0 (no limit).  Example: WLFTimeLimit = {100 ms}
+; WLFTimeLimit = 0
+
+; WLF file size limit.  Limit WLF file size, as closely as possible,
+; to the specified number of megabytes.  If both time and size limits
+; are specified then the most restrictive is used.
+; The default is 0 (no limit).
+; WLFSizeLimit = 1000
+
+; Specify whether or not a WLF file should be deleted when the
+; simulation ends.  A value of 1 will cause the WLF file to be deleted.
+; The default is 0 (do not delete WLF file when simulation ends).
+; WLFDeleteOnQuit = 1
+
+; Automatic SDF compilation
+; Disables automatic compilation of SDF files in flows that support it.
+; Default is on, uncomment to turn off.
+; NoAutoSDFCompile = 1
+
+[lmc]
+
+[msg_system]
+; Change a message severity or suppress a message.
+; The format is: <msg directive> = <msg number>[,<msg number>...]
+; Examples:
+;   note = 3009
+;   warning = 3033
+;   error = 3010,3016
+;   fatal = 3016,3033
+;   suppress = 3009,3016,3043
+; The command verror <msg number> can be used to get the complete
+; description of a message.
+
+; Control transcripting of elaboration/runtime messages.
+; The default is to have messages appear in the transcript and 
+; recorded in the wlf file (messages that are recorded in the
+; wlf file can be viewed in the MsgViewer).  The other settings
+; are to send messages only to the transcript or only to the 
+; wlf file.  The valid values are
+;    both  {default}
+;    tran  {transcript only}
+;    wlf   {wlf file only}
+; msgmode = both
+[Project]
+** Warning: ; Warning -- Do not edit the project properties directly.
+;            Property names are dynamic in nature and property
+;            values have special syntax.  Changing property data directly
+;            can result in a corrupt MPF file.  All project properties
+;            can be modified through project window dialogs.
+Project_Version = 6
+Project_DefaultLib = work
+Project_SortMethod = unused
+Project_Files_Count = 2
+Project_File_0 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/alu.sv
+Project_File_P_0 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1789355084 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 vlog_showsource 0 vlog_hazard 0 cover_optlevel 3 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 0 cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_1 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/alu_tb.sv
+Project_File_P_1 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1789355084 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 vlog_showsource 0 vlog_hazard 0 cover_optlevel 3 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 1 cover_expr 0 dont_compile 0 cover_stmt 0
+Project_Sim_Count = 0
+Project_Folder_Count = 0
+Echo_Compile_Output = 0
+Save_Compile_Report = 1
+Project_Opt_Count = 0
+ForceSoftPaths = 0
+ProjectStatusDelay = 5000
+VERILOG_DoubleClick = Edit
+VERILOG_CustomDoubleClick = 
+SYSTEMVERILOG_DoubleClick = Edit
+SYSTEMVERILOG_CustomDoubleClick = 
+VHDL_DoubleClick = Edit
+VHDL_CustomDoubleClick = 
+PSL_DoubleClick = Edit
+PSL_CustomDoubleClick = 
+TEXT_DoubleClick = Edit
+TEXT_CustomDoubleClick = 
+SYSTEMC_DoubleClick = Edit
+SYSTEMC_CustomDoubleClick = 
+TCL_DoubleClick = Edit
+TCL_CustomDoubleClick = 
+MACRO_DoubleClick = Edit
+MACRO_CustomDoubleClick = 
+VCD_DoubleClick = Edit
+VCD_CustomDoubleClick = 
+SDF_DoubleClick = Edit
+SDF_CustomDoubleClick = 
+XML_DoubleClick = Edit
+XML_CustomDoubleClick = 
+LOGFILE_DoubleClick = Edit
+LOGFILE_CustomDoubleClick = 
+UCDB_DoubleClick = Edit
+UCDB_CustomDoubleClick = 
+TDB_DoubleClick = Edit
+TDB_CustomDoubleClick = 
+UPF_DoubleClick = Edit
+UPF_CustomDoubleClick = 
+PCF_DoubleClick = Edit
+PCF_CustomDoubleClick = 
+PROJECT_DoubleClick = Edit
+PROJECT_CustomDoubleClick = 
+VRM_DoubleClick = Edit
+VRM_CustomDoubleClick = 
+DEBUGDATABASE_DoubleClick = Edit
+DEBUGDATABASE_CustomDoubleClick = 
+DEBUGARCHIVE_DoubleClick = Edit
+DEBUGARCHIVE_CustomDoubleClick = 
+Project_Major_Version = 2020
+Project_Minor_Version = 1

ModelSim/Assignment_1_Q5.cr.mti

@@ -0,0 +1,16 @@
+/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/shifter.sv {1 {vlog -work work -sv -stats=none /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/shifter.sv
+Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
+-- Compiling module shifter
+
+Top level modules:
+	shifter
+
+} {} {}} /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/shifter_tb.sv {1 {vlog -work work -sv -stats=none /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/shifter_tb.sv
+Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
+-- Compiling module shifter
+-- Compiling module shifter_tb
+
+Top level modules:
+	shifter_tb
+
+} {} {}}

ModelSim/Assignment_1_Q5.mpf

@@ -0,0 +1,466 @@
+; Copyright 1991-2009 Mentor Graphics Corporation
+;
+; All Rights Reserved.
+;
+; THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH IS THE PROPERTY OF 
+; MENTOR GRAPHICS CORPORATION OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS.
+;   
+
+[Library]
+std = $MODEL_TECH/../std
+ieee = $MODEL_TECH/../ieee
+verilog = $MODEL_TECH/../verilog
+vital2000 = $MODEL_TECH/../vital2000
+std_developerskit = $MODEL_TECH/../std_developerskit
+synopsys = $MODEL_TECH/../synopsys
+modelsim_lib = $MODEL_TECH/../modelsim_lib
+sv_std = $MODEL_TECH/../sv_std
+
+; Altera Primitive libraries
+;
+; VHDL Section
+;
+altera_mf = $MODEL_TECH/../altera/vhdl/altera_mf
+altera = $MODEL_TECH/../altera/vhdl/altera
+altera_lnsim = $MODEL_TECH/../altera/vhdl/altera_lnsim
+lpm = $MODEL_TECH/../altera/vhdl/220model
+220model = $MODEL_TECH/../altera/vhdl/220model
+maxii = $MODEL_TECH/../altera/vhdl/maxii
+maxv = $MODEL_TECH/../altera/vhdl/maxv
+fiftyfivenm = $MODEL_TECH/../altera/vhdl/fiftyfivenm
+sgate = $MODEL_TECH/../altera/vhdl/sgate
+arriaii = $MODEL_TECH/../altera/vhdl/arriaii
+arriaii_hssi = $MODEL_TECH/../altera/vhdl/arriaii_hssi
+arriaii_pcie_hip = $MODEL_TECH/../altera/vhdl/arriaii_pcie_hip
+arriaiigz = $MODEL_TECH/../altera/vhdl/arriaiigz
+arriaiigz_hssi = $MODEL_TECH/../altera/vhdl/arriaiigz_hssi
+arriaiigz_pcie_hip = $MODEL_TECH/../altera/vhdl/arriaiigz_pcie_hip
+stratixiv = $MODEL_TECH/../altera/vhdl/stratixiv
+stratixiv_hssi = $MODEL_TECH/../altera/vhdl/stratixiv_hssi
+stratixiv_pcie_hip = $MODEL_TECH/../altera/vhdl/stratixiv_pcie_hip
+cycloneiv = $MODEL_TECH/../altera/vhdl/cycloneiv
+cycloneiv_hssi = $MODEL_TECH/../altera/vhdl/cycloneiv_hssi
+cycloneiv_pcie_hip = $MODEL_TECH/../altera/vhdl/cycloneiv_pcie_hip
+cycloneive = $MODEL_TECH/../altera/vhdl/cycloneive
+stratixv = $MODEL_TECH/../altera/vhdl/stratixv
+stratixv_hssi = $MODEL_TECH/../altera/vhdl/stratixv_hssi
+stratixv_pcie_hip = $MODEL_TECH/../altera/vhdl/stratixv_pcie_hip
+arriavgz = $MODEL_TECH/../altera/vhdl/arriavgz
+arriavgz_hssi = $MODEL_TECH/../altera/vhdl/arriavgz_hssi
+arriavgz_pcie_hip = $MODEL_TECH/../altera/vhdl/arriavgz_pcie_hip
+arriav = $MODEL_TECH/../altera/vhdl/arriav
+cyclonev = $MODEL_TECH/../altera/vhdl/cyclonev
+twentynm = $MODEL_TECH/../altera/vhdl/twentynm
+twentynm_hssi = $MODEL_TECH/../altera/vhdl/twentynm_hssi
+twentynm_hip = $MODEL_TECH/../altera/vhdl/twentynm_hip
+cyclone10lp = $MODEL_TECH/../altera/vhdl/cyclone10lp
+;
+; Verilog Section
+;
+altera_mf_ver = $MODEL_TECH/../altera/verilog/altera_mf
+altera_ver = $MODEL_TECH/../altera/verilog/altera
+altera_lnsim_ver = $MODEL_TECH/../altera/verilog/altera_lnsim
+lpm_ver = $MODEL_TECH/../altera/verilog/220model
+220model_ver = $MODEL_TECH/../altera/verilog/220model
+maxii_ver = $MODEL_TECH/../altera/verilog/maxii
+maxv_ver = $MODEL_TECH/../altera/verilog/maxv
+fiftyfivenm_ver = $MODEL_TECH/../altera/verilog/fiftyfivenm
+sgate_ver = $MODEL_TECH/../altera/verilog/sgate
+arriaii_ver = $MODEL_TECH/../altera/verilog/arriaii
+arriaii_hssi_ver = $MODEL_TECH/../altera/verilog/arriaii_hssi
+arriaii_pcie_hip_ver = $MODEL_TECH/../altera/verilog/arriaii_pcie_hip
+arriaiigz_ver = $MODEL_TECH/../altera/verilog/arriaiigz
+arriaiigz_hssi_ver = $MODEL_TECH/../altera/verilog/arriaiigz_hssi
+arriaiigz_pcie_hip_ver = $MODEL_TECH/../altera/verilog/arriaiigz_pcie_hip
+stratixiv_ver = $MODEL_TECH/../altera/verilog/stratixiv
+stratixiv_hssi_ver = $MODEL_TECH/../altera/verilog/stratixiv_hssi
+stratixiv_pcie_hip_ver = $MODEL_TECH/../altera/verilog/stratixiv_pcie_hip
+stratixv_ver = $MODEL_TECH/../altera/verilog/stratixv
+stratixv_hssi_ver = $MODEL_TECH/../altera/verilog/stratixv_hssi
+stratixv_pcie_hip_ver = $MODEL_TECH/../altera/verilog/stratixv_pcie_hip
+arriavgz_ver = $MODEL_TECH/../altera/verilog/arriavgz
+arriavgz_hssi_ver = $MODEL_TECH/../altera/verilog/arriavgz_hssi
+arriavgz_pcie_hip_ver = $MODEL_TECH/../altera/verilog/arriavgz_pcie_hip
+arriav_ver = $MODEL_TECH/../altera/verilog/arriav
+arriav_hssi_ver = $MODEL_TECH/../altera/verilog/arriav_hssi
+arriav_pcie_hip_ver = $MODEL_TECH/../altera/verilog/arriav_pcie_hip
+cyclonev_ver = $MODEL_TECH/../altera/verilog/cyclonev
+cyclonev_hssi_ver = $MODEL_TECH/../altera/verilog/cyclonev_hssi
+cyclonev_pcie_hip_ver = $MODEL_TECH/../altera/verilog/cyclonev_pcie_hip
+cycloneiv_ver = $MODEL_TECH/../altera/verilog/cycloneiv
+cycloneiv_hssi_ver = $MODEL_TECH/../altera/verilog/cycloneiv_hssi
+cycloneiv_pcie_hip_ver = $MODEL_TECH/../altera/verilog/cycloneiv_pcie_hip
+cycloneive_ver = $MODEL_TECH/../altera/verilog/cycloneive
+twentynm_ver = $MODEL_TECH/../altera/verilog/twentynm
+twentynm_hssi_ver = $MODEL_TECH/../altera/verilog/twentynm_hssi
+twentynm_hip_ver = $MODEL_TECH/../altera/verilog/twentynm_hip
+cyclone10lp_ver = $MODEL_TECH/../altera/verilog/cyclone10lp
+
+work = work
+[vcom]
+; VHDL93 variable selects language version as the default. 
+; Default is VHDL-2002.
+; Value of 0 or 1987 for VHDL-1987.
+; Value of 1 or 1993 for VHDL-1993.
+; Default or value of 2 or 2002 for VHDL-2002.
+; Default or value of 3 or 2008 for VHDL-2008.
+VHDL93 = 2002
+
+; Show source line containing error. Default is off.
+; Show_source = 1
+
+; Turn off unbound-component warnings. Default is on.
+; Show_Warning1 = 0
+
+; Turn off process-without-a-wait-statement warnings. Default is on.
+; Show_Warning2 = 0
+
+; Turn off null-range warnings. Default is on.
+; Show_Warning3 = 0
+
+; Turn off no-space-in-time-literal warnings. Default is on.
+; Show_Warning4 = 0
+
+; Turn off multiple-drivers-on-unresolved-signal warnings. Default is on.
+; Show_Warning5 = 0
+
+; Turn off optimization for IEEE std_logic_1164 package. Default is on.
+; Optimize_1164 = 0
+
+; Turn on resolving of ambiguous function overloading in favor of the
+; "explicit" function declaration (not the one automatically created by
+; the compiler for each type declaration). Default is off.
+; The .ini file has Explicit enabled so that std_logic_signed/unsigned
+; will match the behavior of synthesis tools.
+Explicit = 1
+
+; Turn off acceleration of the VITAL packages. Default is to accelerate.
+; NoVital = 1
+
+; Turn off VITAL compliance checking. Default is checking on.
+; NoVitalCheck = 1
+
+; Ignore VITAL compliance checking errors. Default is to not ignore.
+; IgnoreVitalErrors = 1
+
+; Turn off VITAL compliance checking warnings. Default is to show warnings.
+; Show_VitalChecksWarnings = 0
+
+; Keep silent about case statement static warnings.
+; Default is to give a warning.
+; NoCaseStaticError = 1
+
+; Keep silent about warnings caused by aggregates that are not locally static.
+; Default is to give a warning.
+; NoOthersStaticError = 1
+
+; Turn off inclusion of debugging info within design units.
+; Default is to include debugging info.
+; NoDebug = 1
+
+; Turn off "Loading..." messages. Default is messages on.
+; Quiet = 1
+
+; Turn on some limited synthesis rule compliance checking. Checks only:
+;    -- signals used (read) by a process must be in the sensitivity list
+; CheckSynthesis = 1
+
+; Activate optimizations on expressions that do not involve signals,
+; waits, or function/procedure/task invocations. Default is off.
+; ScalarOpts = 1
+
+; Require the user to specify a configuration for all bindings,
+; and do not generate a compile time default binding for the
+; component. This will result in an elaboration error of
+; 'component not bound' if the user fails to do so. Avoids the rare
+; issue of a false dependency upon the unused default binding.
+; RequireConfigForAllDefaultBinding = 1
+
+; Inhibit range checking on subscripts of arrays. Range checking on
+; scalars defined with subtypes is inhibited by default.
+; NoIndexCheck = 1
+
+; Inhibit range checks on all (implicit and explicit) assignments to
+; scalar objects defined with subtypes.
+; NoRangeCheck = 1
+
+[vlog]
+
+; Turn off inclusion of debugging info within design units.
+; Default is to include debugging info.
+; NoDebug = 1
+
+; Turn off "loading..." messages. Default is messages on.
+; Quiet = 1
+
+; Turn on Verilog hazard checking (order-dependent accessing of global vars).
+; Default is off.
+; Hazard = 1
+
+; Turn on converting regular Verilog identifiers to uppercase. Allows case
+; insensitivity for module names. Default is no conversion.
+; UpCase = 1
+
+; Turn on incremental compilation of modules. Default is off.
+; Incremental = 1
+
+; Turns on lint-style checking.
+; Show_Lint = 1
+
+[vsim]
+; Simulator resolution
+; Set to fs, ps, ns, us, ms, or sec with optional prefix of 1, 10, or 100.
+Resolution = ps
+
+; User time unit for run commands
+; Set to default, fs, ps, ns, us, ms, or sec. The default is to use the
+; unit specified for Resolution. For example, if Resolution is 100ps,
+; then UserTimeUnit defaults to ps.
+; Should generally be set to default.
+UserTimeUnit = default
+
+; Default run length
+RunLength = 100 ps
+
+; Maximum iterations that can be run without advancing simulation time
+IterationLimit = 5000
+
+; Directive to license manager:
+; vhdl          Immediately reserve a VHDL license
+; vlog          Immediately reserve a Verilog license
+; plus          Immediately reserve a VHDL and Verilog license
+; nomgc         Do not look for Mentor Graphics Licenses
+; nomti         Do not look for Model Technology Licenses
+; noqueue       Do not wait in the license queue when a license isn't available
+; viewsim	Try for viewer license but accept simulator license(s) instead
+;		of queuing for viewer license
+; License = plus
+
+; Stop the simulator after a VHDL/Verilog assertion message
+; 0 = Note  1 = Warning  2 = Error  3 = Failure  4 = Fatal
+BreakOnAssertion = 3
+
+; Assertion Message Format
+; %S - Severity Level 
+; %R - Report Message
+; %T - Time of assertion
+; %D - Delta
+; %I - Instance or Region pathname (if available)
+; %% - print '%' character
+; AssertionFormat = "** %S: %R\n   Time: %T  Iteration: %D%I\n"
+
+; Assertion File - alternate file for storing VHDL/Verilog assertion messages
+; AssertFile = assert.log
+
+; Default radix for all windows and commands...
+; Set to symbolic, ascii, binary, octal, decimal, hex, unsigned
+DefaultRadix = symbolic
+
+; VSIM Startup command
+; Startup = do startup.do
+
+; File for saving command transcript
+TranscriptFile = transcript
+
+; File for saving command history
+; CommandHistory = cmdhist.log
+
+; Specify whether paths in simulator commands should be described
+; in VHDL or Verilog format.
+; For VHDL, PathSeparator = /
+; For Verilog, PathSeparator = .
+; Must not be the same character as DatasetSeparator.
+PathSeparator = /
+
+; Specify the dataset separator for fully rooted contexts.
+; The default is ':'. For example, sim:/top
+; Must not be the same character as PathSeparator.
+DatasetSeparator = :
+
+; Disable VHDL assertion messages
+; IgnoreNote = 1
+; IgnoreWarning = 1
+; IgnoreError = 1
+; IgnoreFailure = 1
+
+; Default force kind. May be freeze, drive, deposit, or default
+; or in other terms, fixed, wired, or charged.
+; A value of "default" will use the signal kind to determine the
+; force kind, drive for resolved signals, freeze for unresolved signals
+; DefaultForceKind = freeze
+
+; If zero, open files when elaborated; otherwise, open files on
+; first read or write.  Default is 0.
+; DelayFileOpen = 1
+
+; Control VHDL files opened for write.
+;   0 = Buffered, 1 = Unbuffered
+UnbufferedOutput = 0
+
+; Control the number of VHDL files open concurrently.
+; This number should always be less than the current ulimit
+; setting for max file descriptors.
+;   0 = unlimited
+ConcurrentFileLimit = 40
+
+; Control the number of hierarchical regions displayed as
+; part of a signal name shown in the Wave window.
+; A value of zero tells VSIM to display the full name.
+; The default is 0.
+; WaveSignalNameWidth = 0
+
+; Turn off warnings from the std_logic_arith, std_logic_unsigned
+; and std_logic_signed packages.
+; StdArithNoWarnings = 1
+
+; Turn off warnings from the IEEE numeric_std and numeric_bit packages.
+; NumericStdNoWarnings = 1
+
+; Control the format of the (VHDL) FOR generate statement label
+; for each iteration.  Do not quote it.
+; The format string here must contain the conversion codes %s and %d,
+; in that order, and no other conversion codes.  The %s represents
+; the generate_label; the %d represents the generate parameter value
+; at a particular generate iteration (this is the position number if
+; the generate parameter is of an enumeration type).  Embedded whitespace
+; is allowed (but discouraged); leading and trailing whitespace is ignored.
+; Application of the format must result in a unique scope name over all
+; such names in the design so that name lookup can function properly.
+; GenerateFormat = %s__%d
+
+; Specify whether checkpoint files should be compressed.
+; The default is 1 (compressed).
+; CheckpointCompressMode = 0
+
+; List of dynamically loaded objects for Verilog PLI applications
+; Veriuser = veriuser.sl
+
+; Specify default options for the restart command. Options can be one
+; or more of: -force -nobreakpoint -nolist -nolog -nowave
+; DefaultRestartOptions = -force
+
+; HP-UX 10.20 ONLY - Enable memory locking to speed up large designs
+; (> 500 megabyte memory footprint). Default is disabled.
+; Specify number of megabytes to lock.
+; LockedMemory = 1000
+
+; Turn on (1) or off (0) WLF file compression.
+; The default is 1 (compress WLF file).
+; WLFCompress = 0
+
+; Specify whether to save all design hierarchy (1) in the WLF file
+; or only regions containing logged signals (0).
+; The default is 0 (save only regions with logged signals).
+; WLFSaveAllRegions = 1
+
+; WLF file time limit.  Limit WLF file by time, as closely as possible,
+; to the specified amount of simulation time.  When the limit is exceeded
+; the earliest times get truncated from the file.
+; If both time and size limits are specified the most restrictive is used.
+; UserTimeUnits are used if time units are not specified.
+; The default is 0 (no limit).  Example: WLFTimeLimit = {100 ms}
+; WLFTimeLimit = 0
+
+; WLF file size limit.  Limit WLF file size, as closely as possible,
+; to the specified number of megabytes.  If both time and size limits
+; are specified then the most restrictive is used.
+; The default is 0 (no limit).
+; WLFSizeLimit = 1000
+
+; Specify whether or not a WLF file should be deleted when the
+; simulation ends.  A value of 1 will cause the WLF file to be deleted.
+; The default is 0 (do not delete WLF file when simulation ends).
+; WLFDeleteOnQuit = 1
+
+; Automatic SDF compilation
+; Disables automatic compilation of SDF files in flows that support it.
+; Default is on, uncomment to turn off.
+; NoAutoSDFCompile = 1
+
+[lmc]
+
+[msg_system]
+; Change a message severity or suppress a message.
+; The format is: <msg directive> = <msg number>[,<msg number>...]
+; Examples:
+;   note = 3009
+;   warning = 3033
+;   error = 3010,3016
+;   fatal = 3016,3033
+;   suppress = 3009,3016,3043
+; The command verror <msg number> can be used to get the complete
+; description of a message.
+
+; Control transcripting of elaboration/runtime messages.
+; The default is to have messages appear in the transcript and 
+; recorded in the wlf file (messages that are recorded in the
+; wlf file can be viewed in the MsgViewer).  The other settings
+; are to send messages only to the transcript or only to the 
+; wlf file.  The valid values are
+;    both  {default}
+;    tran  {transcript only}
+;    wlf   {wlf file only}
+; msgmode = both
+[Project]
+** Warning: ; Warning -- Do not edit the project properties directly.
+;            Property names are dynamic in nature and property
+;            values have special syntax.  Changing property data directly
+;            can result in a corrupt MPF file.  All project properties
+;            can be modified through project window dialogs.
+Project_Version = 6
+Project_DefaultLib = work
+Project_SortMethod = unused
+Project_Files_Count = 2
+Project_File_0 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/shifter.sv
+Project_File_P_0 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1789355084 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 vlog_showsource 0 vlog_hazard 0 cover_optlevel 3 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 0 cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_1 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/shifter_tb.sv
+Project_File_P_1 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1788926090 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 vlog_showsource 0 vlog_hazard 0 cover_optlevel 3 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 1 cover_expr 0 dont_compile 0 cover_stmt 0
+Project_Sim_Count = 0
+Project_Folder_Count = 0
+Echo_Compile_Output = 0
+Save_Compile_Report = 1
+Project_Opt_Count = 0
+ForceSoftPaths = 0
+ProjectStatusDelay = 5000
+VERILOG_DoubleClick = Edit
+VERILOG_CustomDoubleClick = 
+SYSTEMVERILOG_DoubleClick = Edit
+SYSTEMVERILOG_CustomDoubleClick = 
+VHDL_DoubleClick = Edit
+VHDL_CustomDoubleClick = 
+PSL_DoubleClick = Edit
+PSL_CustomDoubleClick = 
+TEXT_DoubleClick = Edit
+TEXT_CustomDoubleClick = 
+SYSTEMC_DoubleClick = Edit
+SYSTEMC_CustomDoubleClick = 
+TCL_DoubleClick = Edit
+TCL_CustomDoubleClick = 
+MACRO_DoubleClick = Edit
+MACRO_CustomDoubleClick = 
+VCD_DoubleClick = Edit
+VCD_CustomDoubleClick = 
+SDF_DoubleClick = Edit
+SDF_CustomDoubleClick = 
+XML_DoubleClick = Edit
+XML_CustomDoubleClick = 
+LOGFILE_DoubleClick = Edit
+LOGFILE_CustomDoubleClick = 
+UCDB_DoubleClick = Edit
+UCDB_CustomDoubleClick = 
+TDB_DoubleClick = Edit
+TDB_CustomDoubleClick = 
+UPF_DoubleClick = Edit
+UPF_CustomDoubleClick = 
+PCF_DoubleClick = Edit
+PCF_CustomDoubleClick = 
+PROJECT_DoubleClick = Edit
+PROJECT_CustomDoubleClick = 
+VRM_DoubleClick = Edit
+VRM_CustomDoubleClick = 
+DEBUGDATABASE_DoubleClick = Edit
+DEBUGDATABASE_CustomDoubleClick = 
+DEBUGARCHIVE_DoubleClick = Edit
+DEBUGARCHIVE_CustomDoubleClick = 
+Project_Major_Version = 2020
+Project_Minor_Version = 1

ModelSim/Assignment_1_Q6.cr.mti

@@ -0,0 +1,16 @@
+/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/instruction_classifier.sv {1 {vlog -work work -sv -stats=none /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/instruction_classifier.sv
+Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
+-- Compiling module instruction_classifier
+
+Top level modules:
+	instruction_classifier
+
+} {} {}} /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/instruction_classifier_tb.sv {1 {vlog -work work -sv -stats=none /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/instruction_classifier_tb.sv
+Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
+-- Compiling module instruction_classifier
+-- Compiling module instruction_classifier_tb
+
+Top level modules:
+	instruction_classifier_tb
+
+} {} {}}

ModelSim/Assignment_1_Q6.mpf

@@ -0,0 +1,466 @@
+; Copyright 1991-2009 Mentor Graphics Corporation
+;
+; All Rights Reserved.
+;
+; THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH IS THE PROPERTY OF 
+; MENTOR GRAPHICS CORPORATION OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS.
+;   
+
+[Library]
+std = $MODEL_TECH/../std
+ieee = $MODEL_TECH/../ieee
+verilog = $MODEL_TECH/../verilog
+vital2000 = $MODEL_TECH/../vital2000
+std_developerskit = $MODEL_TECH/../std_developerskit
+synopsys = $MODEL_TECH/../synopsys
+modelsim_lib = $MODEL_TECH/../modelsim_lib
+sv_std = $MODEL_TECH/../sv_std
+
+; Altera Primitive libraries
+;
+; VHDL Section
+;
+altera_mf = $MODEL_TECH/../altera/vhdl/altera_mf
+altera = $MODEL_TECH/../altera/vhdl/altera
+altera_lnsim = $MODEL_TECH/../altera/vhdl/altera_lnsim
+lpm = $MODEL_TECH/../altera/vhdl/220model
+220model = $MODEL_TECH/../altera/vhdl/220model
+maxii = $MODEL_TECH/../altera/vhdl/maxii
+maxv = $MODEL_TECH/../altera/vhdl/maxv
+fiftyfivenm = $MODEL_TECH/../altera/vhdl/fiftyfivenm
+sgate = $MODEL_TECH/../altera/vhdl/sgate
+arriaii = $MODEL_TECH/../altera/vhdl/arriaii
+arriaii_hssi = $MODEL_TECH/../altera/vhdl/arriaii_hssi
+arriaii_pcie_hip = $MODEL_TECH/../altera/vhdl/arriaii_pcie_hip
+arriaiigz = $MODEL_TECH/../altera/vhdl/arriaiigz
+arriaiigz_hssi = $MODEL_TECH/../altera/vhdl/arriaiigz_hssi
+arriaiigz_pcie_hip = $MODEL_TECH/../altera/vhdl/arriaiigz_pcie_hip
+stratixiv = $MODEL_TECH/../altera/vhdl/stratixiv
+stratixiv_hssi = $MODEL_TECH/../altera/vhdl/stratixiv_hssi
+stratixiv_pcie_hip = $MODEL_TECH/../altera/vhdl/stratixiv_pcie_hip
+cycloneiv = $MODEL_TECH/../altera/vhdl/cycloneiv
+cycloneiv_hssi = $MODEL_TECH/../altera/vhdl/cycloneiv_hssi
+cycloneiv_pcie_hip = $MODEL_TECH/../altera/vhdl/cycloneiv_pcie_hip
+cycloneive = $MODEL_TECH/../altera/vhdl/cycloneive
+stratixv = $MODEL_TECH/../altera/vhdl/stratixv
+stratixv_hssi = $MODEL_TECH/../altera/vhdl/stratixv_hssi
+stratixv_pcie_hip = $MODEL_TECH/../altera/vhdl/stratixv_pcie_hip
+arriavgz = $MODEL_TECH/../altera/vhdl/arriavgz
+arriavgz_hssi = $MODEL_TECH/../altera/vhdl/arriavgz_hssi
+arriavgz_pcie_hip = $MODEL_TECH/../altera/vhdl/arriavgz_pcie_hip
+arriav = $MODEL_TECH/../altera/vhdl/arriav
+cyclonev = $MODEL_TECH/../altera/vhdl/cyclonev
+twentynm = $MODEL_TECH/../altera/vhdl/twentynm
+twentynm_hssi = $MODEL_TECH/../altera/vhdl/twentynm_hssi
+twentynm_hip = $MODEL_TECH/../altera/vhdl/twentynm_hip
+cyclone10lp = $MODEL_TECH/../altera/vhdl/cyclone10lp
+;
+; Verilog Section
+;
+altera_mf_ver = $MODEL_TECH/../altera/verilog/altera_mf
+altera_ver = $MODEL_TECH/../altera/verilog/altera
+altera_lnsim_ver = $MODEL_TECH/../altera/verilog/altera_lnsim
+lpm_ver = $MODEL_TECH/../altera/verilog/220model
+220model_ver = $MODEL_TECH/../altera/verilog/220model
+maxii_ver = $MODEL_TECH/../altera/verilog/maxii
+maxv_ver = $MODEL_TECH/../altera/verilog/maxv
+fiftyfivenm_ver = $MODEL_TECH/../altera/verilog/fiftyfivenm
+sgate_ver = $MODEL_TECH/../altera/verilog/sgate
+arriaii_ver = $MODEL_TECH/../altera/verilog/arriaii
+arriaii_hssi_ver = $MODEL_TECH/../altera/verilog/arriaii_hssi
+arriaii_pcie_hip_ver = $MODEL_TECH/../altera/verilog/arriaii_pcie_hip
+arriaiigz_ver = $MODEL_TECH/../altera/verilog/arriaiigz
+arriaiigz_hssi_ver = $MODEL_TECH/../altera/verilog/arriaiigz_hssi
+arriaiigz_pcie_hip_ver = $MODEL_TECH/../altera/verilog/arriaiigz_pcie_hip
+stratixiv_ver = $MODEL_TECH/../altera/verilog/stratixiv
+stratixiv_hssi_ver = $MODEL_TECH/../altera/verilog/stratixiv_hssi
+stratixiv_pcie_hip_ver = $MODEL_TECH/../altera/verilog/stratixiv_pcie_hip
+stratixv_ver = $MODEL_TECH/../altera/verilog/stratixv
+stratixv_hssi_ver = $MODEL_TECH/../altera/verilog/stratixv_hssi
+stratixv_pcie_hip_ver = $MODEL_TECH/../altera/verilog/stratixv_pcie_hip
+arriavgz_ver = $MODEL_TECH/../altera/verilog/arriavgz
+arriavgz_hssi_ver = $MODEL_TECH/../altera/verilog/arriavgz_hssi
+arriavgz_pcie_hip_ver = $MODEL_TECH/../altera/verilog/arriavgz_pcie_hip
+arriav_ver = $MODEL_TECH/../altera/verilog/arriav
+arriav_hssi_ver = $MODEL_TECH/../altera/verilog/arriav_hssi
+arriav_pcie_hip_ver = $MODEL_TECH/../altera/verilog/arriav_pcie_hip
+cyclonev_ver = $MODEL_TECH/../altera/verilog/cyclonev
+cyclonev_hssi_ver = $MODEL_TECH/../altera/verilog/cyclonev_hssi
+cyclonev_pcie_hip_ver = $MODEL_TECH/../altera/verilog/cyclonev_pcie_hip
+cycloneiv_ver = $MODEL_TECH/../altera/verilog/cycloneiv
+cycloneiv_hssi_ver = $MODEL_TECH/../altera/verilog/cycloneiv_hssi
+cycloneiv_pcie_hip_ver = $MODEL_TECH/../altera/verilog/cycloneiv_pcie_hip
+cycloneive_ver = $MODEL_TECH/../altera/verilog/cycloneive
+twentynm_ver = $MODEL_TECH/../altera/verilog/twentynm
+twentynm_hssi_ver = $MODEL_TECH/../altera/verilog/twentynm_hssi
+twentynm_hip_ver = $MODEL_TECH/../altera/verilog/twentynm_hip
+cyclone10lp_ver = $MODEL_TECH/../altera/verilog/cyclone10lp
+
+work = work
+[vcom]
+; VHDL93 variable selects language version as the default. 
+; Default is VHDL-2002.
+; Value of 0 or 1987 for VHDL-1987.
+; Value of 1 or 1993 for VHDL-1993.
+; Default or value of 2 or 2002 for VHDL-2002.
+; Default or value of 3 or 2008 for VHDL-2008.
+VHDL93 = 2002
+
+; Show source line containing error. Default is off.
+; Show_source = 1
+
+; Turn off unbound-component warnings. Default is on.
+; Show_Warning1 = 0
+
+; Turn off process-without-a-wait-statement warnings. Default is on.
+; Show_Warning2 = 0
+
+; Turn off null-range warnings. Default is on.
+; Show_Warning3 = 0
+
+; Turn off no-space-in-time-literal warnings. Default is on.
+; Show_Warning4 = 0
+
+; Turn off multiple-drivers-on-unresolved-signal warnings. Default is on.
+; Show_Warning5 = 0
+
+; Turn off optimization for IEEE std_logic_1164 package. Default is on.
+; Optimize_1164 = 0
+
+; Turn on resolving of ambiguous function overloading in favor of the
+; "explicit" function declaration (not the one automatically created by
+; the compiler for each type declaration). Default is off.
+; The .ini file has Explicit enabled so that std_logic_signed/unsigned
+; will match the behavior of synthesis tools.
+Explicit = 1
+
+; Turn off acceleration of the VITAL packages. Default is to accelerate.
+; NoVital = 1
+
+; Turn off VITAL compliance checking. Default is checking on.
+; NoVitalCheck = 1
+
+; Ignore VITAL compliance checking errors. Default is to not ignore.
+; IgnoreVitalErrors = 1
+
+; Turn off VITAL compliance checking warnings. Default is to show warnings.
+; Show_VitalChecksWarnings = 0
+
+; Keep silent about case statement static warnings.
+; Default is to give a warning.
+; NoCaseStaticError = 1
+
+; Keep silent about warnings caused by aggregates that are not locally static.
+; Default is to give a warning.
+; NoOthersStaticError = 1
+
+; Turn off inclusion of debugging info within design units.
+; Default is to include debugging info.
+; NoDebug = 1
+
+; Turn off "Loading..." messages. Default is messages on.
+; Quiet = 1
+
+; Turn on some limited synthesis rule compliance checking. Checks only:
+;    -- signals used (read) by a process must be in the sensitivity list
+; CheckSynthesis = 1
+
+; Activate optimizations on expressions that do not involve signals,
+; waits, or function/procedure/task invocations. Default is off.
+; ScalarOpts = 1
+
+; Require the user to specify a configuration for all bindings,
+; and do not generate a compile time default binding for the
+; component. This will result in an elaboration error of
+; 'component not bound' if the user fails to do so. Avoids the rare
+; issue of a false dependency upon the unused default binding.
+; RequireConfigForAllDefaultBinding = 1
+
+; Inhibit range checking on subscripts of arrays. Range checking on
+; scalars defined with subtypes is inhibited by default.
+; NoIndexCheck = 1
+
+; Inhibit range checks on all (implicit and explicit) assignments to
+; scalar objects defined with subtypes.
+; NoRangeCheck = 1
+
+[vlog]
+
+; Turn off inclusion of debugging info within design units.
+; Default is to include debugging info.
+; NoDebug = 1
+
+; Turn off "loading..." messages. Default is messages on.
+; Quiet = 1
+
+; Turn on Verilog hazard checking (order-dependent accessing of global vars).
+; Default is off.
+; Hazard = 1
+
+; Turn on converting regular Verilog identifiers to uppercase. Allows case
+; insensitivity for module names. Default is no conversion.
+; UpCase = 1
+
+; Turn on incremental compilation of modules. Default is off.
+; Incremental = 1
+
+; Turns on lint-style checking.
+; Show_Lint = 1
+
+[vsim]
+; Simulator resolution
+; Set to fs, ps, ns, us, ms, or sec with optional prefix of 1, 10, or 100.
+Resolution = ps
+
+; User time unit for run commands
+; Set to default, fs, ps, ns, us, ms, or sec. The default is to use the
+; unit specified for Resolution. For example, if Resolution is 100ps,
+; then UserTimeUnit defaults to ps.
+; Should generally be set to default.
+UserTimeUnit = default
+
+; Default run length
+RunLength = 100 ps
+
+; Maximum iterations that can be run without advancing simulation time
+IterationLimit = 5000
+
+; Directive to license manager:
+; vhdl          Immediately reserve a VHDL license
+; vlog          Immediately reserve a Verilog license
+; plus          Immediately reserve a VHDL and Verilog license
+; nomgc         Do not look for Mentor Graphics Licenses
+; nomti         Do not look for Model Technology Licenses
+; noqueue       Do not wait in the license queue when a license isn't available
+; viewsim	Try for viewer license but accept simulator license(s) instead
+;		of queuing for viewer license
+; License = plus
+
+; Stop the simulator after a VHDL/Verilog assertion message
+; 0 = Note  1 = Warning  2 = Error  3 = Failure  4 = Fatal
+BreakOnAssertion = 3
+
+; Assertion Message Format
+; %S - Severity Level 
+; %R - Report Message
+; %T - Time of assertion
+; %D - Delta
+; %I - Instance or Region pathname (if available)
+; %% - print '%' character
+; AssertionFormat = "** %S: %R\n   Time: %T  Iteration: %D%I\n"
+
+; Assertion File - alternate file for storing VHDL/Verilog assertion messages
+; AssertFile = assert.log
+
+; Default radix for all windows and commands...
+; Set to symbolic, ascii, binary, octal, decimal, hex, unsigned
+DefaultRadix = symbolic
+
+; VSIM Startup command
+; Startup = do startup.do
+
+; File for saving command transcript
+TranscriptFile = transcript
+
+; File for saving command history
+; CommandHistory = cmdhist.log
+
+; Specify whether paths in simulator commands should be described
+; in VHDL or Verilog format.
+; For VHDL, PathSeparator = /
+; For Verilog, PathSeparator = .
+; Must not be the same character as DatasetSeparator.
+PathSeparator = /
+
+; Specify the dataset separator for fully rooted contexts.
+; The default is ':'. For example, sim:/top
+; Must not be the same character as PathSeparator.
+DatasetSeparator = :
+
+; Disable VHDL assertion messages
+; IgnoreNote = 1
+; IgnoreWarning = 1
+; IgnoreError = 1
+; IgnoreFailure = 1
+
+; Default force kind. May be freeze, drive, deposit, or default
+; or in other terms, fixed, wired, or charged.
+; A value of "default" will use the signal kind to determine the
+; force kind, drive for resolved signals, freeze for unresolved signals
+; DefaultForceKind = freeze
+
+; If zero, open files when elaborated; otherwise, open files on
+; first read or write.  Default is 0.
+; DelayFileOpen = 1
+
+; Control VHDL files opened for write.
+;   0 = Buffered, 1 = Unbuffered
+UnbufferedOutput = 0
+
+; Control the number of VHDL files open concurrently.
+; This number should always be less than the current ulimit
+; setting for max file descriptors.
+;   0 = unlimited
+ConcurrentFileLimit = 40
+
+; Control the number of hierarchical regions displayed as
+; part of a signal name shown in the Wave window.
+; A value of zero tells VSIM to display the full name.
+; The default is 0.
+; WaveSignalNameWidth = 0
+
+; Turn off warnings from the std_logic_arith, std_logic_unsigned
+; and std_logic_signed packages.
+; StdArithNoWarnings = 1
+
+; Turn off warnings from the IEEE numeric_std and numeric_bit packages.
+; NumericStdNoWarnings = 1
+
+; Control the format of the (VHDL) FOR generate statement label
+; for each iteration.  Do not quote it.
+; The format string here must contain the conversion codes %s and %d,
+; in that order, and no other conversion codes.  The %s represents
+; the generate_label; the %d represents the generate parameter value
+; at a particular generate iteration (this is the position number if
+; the generate parameter is of an enumeration type).  Embedded whitespace
+; is allowed (but discouraged); leading and trailing whitespace is ignored.
+; Application of the format must result in a unique scope name over all
+; such names in the design so that name lookup can function properly.
+; GenerateFormat = %s__%d
+
+; Specify whether checkpoint files should be compressed.
+; The default is 1 (compressed).
+; CheckpointCompressMode = 0
+
+; List of dynamically loaded objects for Verilog PLI applications
+; Veriuser = veriuser.sl
+
+; Specify default options for the restart command. Options can be one
+; or more of: -force -nobreakpoint -nolist -nolog -nowave
+; DefaultRestartOptions = -force
+
+; HP-UX 10.20 ONLY - Enable memory locking to speed up large designs
+; (> 500 megabyte memory footprint). Default is disabled.
+; Specify number of megabytes to lock.
+; LockedMemory = 1000
+
+; Turn on (1) or off (0) WLF file compression.
+; The default is 1 (compress WLF file).
+; WLFCompress = 0
+
+; Specify whether to save all design hierarchy (1) in the WLF file
+; or only regions containing logged signals (0).
+; The default is 0 (save only regions with logged signals).
+; WLFSaveAllRegions = 1
+
+; WLF file time limit.  Limit WLF file by time, as closely as possible,
+; to the specified amount of simulation time.  When the limit is exceeded
+; the earliest times get truncated from the file.
+; If both time and size limits are specified the most restrictive is used.
+; UserTimeUnits are used if time units are not specified.
+; The default is 0 (no limit).  Example: WLFTimeLimit = {100 ms}
+; WLFTimeLimit = 0
+
+; WLF file size limit.  Limit WLF file size, as closely as possible,
+; to the specified number of megabytes.  If both time and size limits
+; are specified then the most restrictive is used.
+; The default is 0 (no limit).
+; WLFSizeLimit = 1000
+
+; Specify whether or not a WLF file should be deleted when the
+; simulation ends.  A value of 1 will cause the WLF file to be deleted.
+; The default is 0 (do not delete WLF file when simulation ends).
+; WLFDeleteOnQuit = 1
+
+; Automatic SDF compilation
+; Disables automatic compilation of SDF files in flows that support it.
+; Default is on, uncomment to turn off.
+; NoAutoSDFCompile = 1
+
+[lmc]
+
+[msg_system]
+; Change a message severity or suppress a message.
+; The format is: <msg directive> = <msg number>[,<msg number>...]
+; Examples:
+;   note = 3009
+;   warning = 3033
+;   error = 3010,3016
+;   fatal = 3016,3033
+;   suppress = 3009,3016,3043
+; The command verror <msg number> can be used to get the complete
+; description of a message.
+
+; Control transcripting of elaboration/runtime messages.
+; The default is to have messages appear in the transcript and 
+; recorded in the wlf file (messages that are recorded in the
+; wlf file can be viewed in the MsgViewer).  The other settings
+; are to send messages only to the transcript or only to the 
+; wlf file.  The valid values are
+;    both  {default}
+;    tran  {transcript only}
+;    wlf   {wlf file only}
+; msgmode = both
+[Project]
+** Warning: ; Warning -- Do not edit the project properties directly.
+;            Property names are dynamic in nature and property
+;            values have special syntax.  Changing property data directly
+;            can result in a corrupt MPF file.  All project properties
+;            can be modified through project window dialogs.
+Project_Version = 6
+Project_DefaultLib = work
+Project_SortMethod = unused
+Project_Files_Count = 2
+Project_File_0 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/instruction_classifier.sv
+Project_File_P_0 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1789355084 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 vlog_showsource 0 vlog_hazard 0 cover_optlevel 3 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 0 cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_1 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/instruction_classifier_tb.sv
+Project_File_P_1 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1789355084 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 vlog_showsource 0 vlog_hazard 0 cover_optlevel 3 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 1 cover_expr 0 dont_compile 0 cover_stmt 0
+Project_Sim_Count = 0
+Project_Folder_Count = 0
+Echo_Compile_Output = 0
+Save_Compile_Report = 1
+Project_Opt_Count = 0
+ForceSoftPaths = 0
+ProjectStatusDelay = 5000
+VERILOG_DoubleClick = Edit
+VERILOG_CustomDoubleClick = 
+SYSTEMVERILOG_DoubleClick = Edit
+SYSTEMVERILOG_CustomDoubleClick = 
+VHDL_DoubleClick = Edit
+VHDL_CustomDoubleClick = 
+PSL_DoubleClick = Edit
+PSL_CustomDoubleClick = 
+TEXT_DoubleClick = Edit
+TEXT_CustomDoubleClick = 
+SYSTEMC_DoubleClick = Edit
+SYSTEMC_CustomDoubleClick = 
+TCL_DoubleClick = Edit
+TCL_CustomDoubleClick = 
+MACRO_DoubleClick = Edit
+MACRO_CustomDoubleClick = 
+VCD_DoubleClick = Edit
+VCD_CustomDoubleClick = 
+SDF_DoubleClick = Edit
+SDF_CustomDoubleClick = 
+XML_DoubleClick = Edit
+XML_CustomDoubleClick = 
+LOGFILE_DoubleClick = Edit
+LOGFILE_CustomDoubleClick = 
+UCDB_DoubleClick = Edit
+UCDB_CustomDoubleClick = 
+TDB_DoubleClick = Edit
+TDB_CustomDoubleClick = 
+UPF_DoubleClick = Edit
+UPF_CustomDoubleClick = 
+PCF_DoubleClick = Edit
+PCF_CustomDoubleClick = 
+PROJECT_DoubleClick = Edit
+PROJECT_CustomDoubleClick = 
+VRM_DoubleClick = Edit
+VRM_CustomDoubleClick = 
+DEBUGDATABASE_DoubleClick = Edit
+DEBUGDATABASE_CustomDoubleClick = 
+DEBUGARCHIVE_DoubleClick = Edit
+DEBUGARCHIVE_CustomDoubleClick = 
+Project_Major_Version = 2020
+Project_Minor_Version = 1

ModelSim/alu.sv

@@ -0,0 +1,37 @@
+`ifndef ALU_H_SV
+`define ALU_H_SV
+
+`include "asu.sv"
+`include "lu.sv"
+
+// flags[0:0] = Cout
+// flags[1:1] = Overflow
+module alu #(parameter width=2)(input logic [3:0] op,
+    input logic [2**width-1:0] A, input logic [2**width-1:0] B,
+    output logic [2**width-1:0] OUT_1, output logic[1:0] flags);
+
+    logic [0:0] asu_op;
+    logic [2**width-1:0] asu_out;
+    logic [1:0] asu_flags;
+    asu #(width) adder_unit(asu_op[op[1]], A, B, asu_out, asu_flags[0], asu_flags[1]);
+
+    logic [2**width-1:0] lu_out;
+    lu #(width) logic_unit(op[1:0], A, B, lu_out);
+
+    always_comb begin
+        case (op) 
+            4'b0000: begin OUT_1 = asu_out; flags = asu_flags; end
+            4'b0001: begin OUT_1 = asu_out; flags = asu_flags; end
+            4'b0010: begin OUT_1 = asu_out; flags = asu_flags; end
+            4'b0011: begin OUT_1 = asu_out; flags = asu_flags; end
+            4'b0100: begin OUT_1 = lu_out; flags = asu_flags; end
+            4'b0101: begin OUT_1 = lu_out; flags = asu_flags; end
+            4'b0110: begin OUT_1 = lu_out;  flags = asu_flags; end
+            4'b0111: begin OUT_1 = lu_out; flags = asu_flags; end
+            4'b1010: begin OUT_1 = (asu_out[2**width-1] ^ asu_flags[1]) & {{(width-1){1'b0}}, 1'b1}; flags = asu_flags; end
+            4'b1011: begin OUT_1 = ~asu_flags[0] & {{(width-1){1'b0}}, 1'b1}; flags = asu_flags; end
+            default: begin OUT_1 = {(2**width){1'b0}}; flags = asu_flags; end
+        endcase
+    end
+endmodule
+`endif

ModelSim/alu_tb.sv

@@ -0,0 +1,216 @@
+`include "alu.sv"
+
+module alu_tb #(width=2)();
+    localparam bitwidth = 2**width;
+
+    // Guard against future me by testing the tests
+    generate
+        if (bitwidth < 4) begin : param_asserts
+            initial begin
+                $fatal(1, "Can not instantiate an ALU testbench with less than 4 bits (n=2)");
+            end
+        end
+    endgenerate
+
+    logic [3:0] op_in;
+    logic [2**width-1:0] A_in;
+    logic [2**width-1:0] B_in;
+    logic [2**width-1:0] Y_out;
+    logic [1:0] flags_out;
+
+    localparam int NUM_TESTS = 28;
+    logic [3:0] ops[NUM_TESTS];
+    logic [2**width-1:0] A_cases[NUM_TESTS];
+    logic [2**width-1:0] B_cases[NUM_TESTS];
+    logic [2**width-1:0] Y_exp[NUM_TESTS];
+    logic [1:0] flags_exp[NUM_TESTS];
+
+    alu #(width) dut (op_in, A_in, B_in, Y_out, flags_out);
+
+    integer error_count;
+    initial begin
+        ops[0] = 4'b0000;                       // sadd
+        A_in[0] = {{(bitwidth-1){1'b0}}, 1'b1};    // 1
+        B_in[0] = {{(bitwidth-1){1'b0}}, 1'b1};    // 1
+        Y_exp[0] = {{(bitwidth-2){1'b0}}, 2'b10};  // 0
+        flags_exp[0] = {2'b00};                 // ~Cout, ~Overflow
+
+        ops[1] = 4'b0000;                       // sadd
+        A_in[1] = {bitwidth{1'b1}};                // UINTMAX
+        B_in[1] = {{(bitwidth-1){1'b0}}, 1'b1};    // 1
+        Y_exp[1] = {bitwidth{1'b0}};               // 0
+        flags_exp[1] = {2'b01};                 // Cout, ~Overflow
+
+        ops[2] = 4'b0000;                       // sadd
+        A_in[2] = {{1'b0}, {(bitwidth-1){1'b1}}};  // INTMAX
+        B_in[2] = {{(bitwidth-1){1'b0}} , {1'b1}}; // 1
+        Y_exp[2] = {{1'b1}, {(bitwidth-1){1'b0}} };// -INTMAX
+        flags_exp[2] = {2'b10};                 // ~Cout, Overflow
+
+        ops[3] = 4'b0000;                       // sadd
+        A_in[3] = {{1'b1}, {(bitwidth-1){1'b0}}};  // -INTMAX
+        B_in[3] = {{1'b1}, {(bitwidth-1){1'b0}}};  // -INTMAX
+        Y_exp[3] = {bitwidth{1'b0}};               // 0
+        flags_exp[3] = {2'b11};                 // Cout, Overflow
+
+        ops[4] = 4'b0001;                       // uadd
+        A_in[4] = {{(bitwidth-1){1'b0}}, 1'b1};    // 1
+        B_in[4] = {{(bitwidth-1){1'b0}}, 1'b1};    // 1
+        Y_exp[4] = {{(bitwidth-2){1'b0}}, 2'b10};  // 0
+        flags_exp[4] = {2'b00};                 // ~Cout, ~Overflow
+
+        ops[5] = 4'b0001;                       // uadd
+        A_in[5] = {bitwidth{1'b1}};                // UINTMAX
+        B_in[5] = {{(bitwidth-1){1'b0}}, 1'b1};    // 1
+        Y_exp[5] = {bitwidth{1'b0}};               // 0
+        flags_exp[5] = {2'b01};                 // Cout, ~Overflow
+
+        ops[6] = 4'b0001;                       // uadd
+        A_in[6] = {{1'b0}, {(bitwidth-1){1'b1}}};  // INTMAX
+        B_in[6] = {{(bitwidth-1){1'b0}} , {1'b1}}; // 1
+        Y_exp[6] = {{1'b1}, {(bitwidth-1){1'b0}} };// -INTMAX
+        flags_exp[6] = {2'b10};                 // ~Cout, Overflow
+
+        ops[7] = 4'b0001;                       // uadd
+        A_in[7] = {{1'b1}, {(bitwidth-1){1'b0}}};  // -INTMAX
+        B_in[7] = {{1'b1}, {(bitwidth-1){1'b0}}};  // -INTMAX
+        Y_exp[7] = {bitwidth{1'b0}};               // 0
+        flags_exp[7] = {2'b11};                 // Cout, Overflow
+
+        ops[8] = 4'b0010;                       // ssub
+        A_in[8] = {{(bitwidth-1){1'b0}}, 1'b1};    // 1
+        B_in[8] = {{(bitwidth-2){1'b0}}, 2'b10};   // 2
+        Y_exp[8] = {bitwidth{1'b1}};               // -1
+        flags_exp[8] = {2'b00};                 // ~Cout, ~Overflow
+
+        ops[9] = 4'b0010;                       // ssub
+        A_in[9] = {1'b0, {(bitwidth-1){1'b1}}};    // INTMAX
+        B_in[9] = {{(bitwidth-1){1'b0}}, 1'b1};    // -1
+        Y_exp[9] = {1'b1, {(bitwidth-1){1'b0}}};   // -INTMAX
+        flags_exp[9] = {2'b10};                 // ~Cout, Overflow
+
+        ops[10] = 4'b0010;                       // ssub
+        A_in[10] = {{(bitwidth-2){1'b0}}, 2'b10};   // 2
+        B_in[10] = {{(bitwidth-1){1'b0}}, 1'b1};    // 1
+        Y_exp[10] = {{(bitwidth-1){1'b0}}, 1'b1};   // 1
+        flags_exp[10] = {2'b01};                 // Cout, ~Overflow
+
+        ops[11] = 4'b0010;                       // ssub
+        A_in[11] = {1'b1, {(bitwidth-1){1'b0}}};    // -INTMAX
+        B_in[11] = {{(bitwidth-1){1'b0}}, 1'b1};    // 1
+        Y_exp[11] = {1'b0, {(bitwidth-1){1'b1}}};   // INTMAX
+        flags_exp[11] = {2'b11};                 // Cout, Overflow
+
+        ops[12] = 4'b0011;                       // ssub
+        A_in[12] = {{(bitwidth-1){1'b0}}, 1'b1};    // 1
+        B_in[12] = {{(bitwidth-2){1'b0}}, 2'b10};   // 2
+        Y_exp[12] = {bitwidth{1'b1}};               // -1
+        flags_exp[12] = {2'b00};                 // ~Cout, ~Overflow
+
+        ops[13] = 4'b0011;                       // ssub
+        A_in[13] = {1'b0, {(bitwidth-1){1'b1}}};    // INTMAX
+        B_in[13] = {{(bitwidth-1){1'b0}}, 1'b1};    // -1
+        Y_exp[13] = {1'b1, {(bitwidth-1){1'b0}}};   // -INTMAX
+        flags_exp[13] = {2'b10};                 // ~Cout, Overflow
+
+        ops[14] = 4'b0011;                       // ssub
+        A_in[14] = {{(bitwidth-2){1'b0}}, 2'b10};   // 2
+        B_in[14] = {{(bitwidth-1){1'b0}}, 1'b1};    // 1
+        Y_exp[14] = {{(bitwidth-1){1'b0}}, 1'b1};   // 1
+        flags_exp[14] = {2'b01};                 // Cout, ~Overflow
+
+        ops[15] = 4'b0011;                       // ssub
+        A_in[15] = {1'b1, {(bitwidth-1){1'b0}}};    // -INTMAX
+        B_in[15] = {{(bitwidth-1){1'b0}}, 1'b1};    // 1
+        Y_exp[15] = {1'b0, {(bitwidth-1){1'b1}}};   // INTMAX
+        flags_exp[15] = {2'b11};                 // Cout, Overflow
+
+        ops[16] = 4'b0100; // and
+        A_in[16] = {{(bitwidth-4){1'b0}}, 4'b1100};    // c
+        B_in[16] = {{(bitwidth-4){1'b0}}, 4'b1010};    // a
+        Y_exp[16] = {{(bitwidth-4){1'b0}}, 4'b1000};   // 8
+        flags_exp[16] = {2'bxx};                    // Don't care
+
+        ops[17] = 4'b0101; // or
+        A_in[17] = {{(bitwidth-4){1'b0}}, 4'b1100};    // c
+        B_in[17] = {{(bitwidth-4){1'b0}}, 4'b1010};    // a
+        Y_exp[17] = {{(bitwidth-4){1'b0}}, 4'b1110};   // e
+        flags_exp[17] = {2'bxx};                    // Don't care
+
+        ops[18] = 4'b0110; // xor
+        A_in[18] = {{(bitwidth-4){1'b0}}, 4'b1100};    // c
+        B_in[18] = {{(bitwidth-4){1'b0}}, 4'b1010};    // a
+        Y_exp[18] = {{(bitwidth-4){1'b0}}, 4'b0110};   // 6
+        flags_exp[18] = {2'bxx};                    // Don't care
+
+        ops[19] = 4'b0111; // nor
+        A_in[19] = {{(bitwidth-4){1'b0}}, 4'b1100};    // c
+        B_in[19] = {{(bitwidth-4){1'b0}}, 4'b1010};    // a
+        Y_exp[19] = {{(bitwidth-4){1'b0}}, 4'b0001};   // 1
+        flags_exp[19] = {2'bxx};                    // Don't care
+
+        ops[20] = 4'b1010;                                      // sslt: 1 < 2 (No overflow)
+        A_in[20] = {{(bitwidth-1){1'b0}}, 1'b1};                   // 1
+        B_in[20] = {{(bitwidth-2){1'b0}}, 2'b10};                  // 2
+        Y_exp[20] = {{(bitwidth-1){1'b0}}, 1'b1};                  // 1 (True)
+        flags_exp[20] = {2'b00};                                // ~Cout, ~Overflow
+
+        ops[21] = 4'b1010;                                      // sslt: 2 < 1 (No overflow)
+        A_in[21] = {{(bitwidth-2){1'b0}}, 2'b10};                  // 2
+        B_in[21] = {{(bitwidth-1){1'b0}}, 1'b1};                   // 1
+        Y_exp[21] = {bitwidth{1'b0}};                              // 0 (False)
+        flags_exp[21] = {2'b10};                                // Cout, ~Overflow
+
+        ops[22] = 4'b1010;                                      // sslt: -INTMAX < 1 (Overflow test)
+        A_in[22] = {1'b1, {(bitwidth-1){1'b0}}};                   // -INTMAX
+        B_in[22] = {{(bitwidth-1){1'b0}}, 1'b1};                   // 1
+        Y_exp[22] = {{(bitwidth-1){1'b0}}, 1'b1};                  // 1 (True)
+        flags_exp[22] = {2'b11};                                // Cout, Overflow
+
+        ops[23] = 4'b1010;                                      // sslt: INTMAX < -1 (Overflow test)
+        A_in[23] = {1'b0, {(bitwidth-1){1'b1}}};                   // INTMAX
+        B_in[23] = {bitwidth{1'b1}};                               // -1
+        Y_exp[23] = {bitwidth{1'b0}};                              // 0 (False)
+        flags_exp[23] = {2'b01};                                // ~Cout, Overflow
+
+        ops[24] = 4'b1011;                                      // uslt: 1 < 2 
+        A_in[24] = {{(bitwidth-1){1'b0}}, 1'b1};                   // 1
+        B_in[24] = {{(bitwidth-2){1'b0}}, 2'b10};                  // 2
+        Y_exp[24] = {{(bitwidth-1){1'b0}}, 1'b1};                  // 1 (True)
+        flags_exp[24] = {2'b00};                                // ~Cout, ~Overflow
+
+        ops[25] = 4'b1011;                                      // uslt: 2 < 1 
+        A_in[25] = {{(bitwidth-2){1'b0}}, 2'b10};                  // 2
+        B_in[25] = {{(bitwidth-1){1'b0}}, 1'b1};                   // 1
+        Y_exp[25] = {bitwidth{1'b0}};                              // 0 (False)
+        flags_exp[25] = {2'b10};                                // Cout, ~Overflow
+
+        ops[26] = 4'b1011;                                      // uslt: 1 < UINTMAX
+        A_in[26] = {{(bitwidth-1){1'b0}}, 1'b1};                   // 1
+        B_in[26] = {bitwidth{1'b1}};                               // UINTMAX
+        Y_exp[26] = {{(bitwidth-1){1'b0}}, 1'b1};                  // 1 (True)
+        flags_exp[26] = {2'b00};                                // ~Cout, ~Overflow
+
+        ops[27] = 4'b1011;                                      // uslt: UINTMAX < 1
+        A_in[27] = {bitwidth{1'b1}};                               // UINTMAX
+        B_in[27] = {{(bitwidth-1){1'b0}}, 1'b1};                   // 1
+        Y_exp[27] = {bitwidth{1'b0}};                              // 0 (False)
+        flags_exp[27] = {2'b10};                                // Cout, ~Overflow
+
+        error_count = 0;
+        $display("Beginning ALU tests");
+        for (integer N = 0; N < $size(ops); ++N) begin
+            op_in = ops[N];
+            A_in = A_cases[N];
+            B_in = B_cases[N];
+            #1;
+            if (Y_out != Y_exp[N]) begin
+                $display("\t\x1b[38;5;9m[%0d] ALU Instruction 0b%b produced 0b%b_%b but 0b%b_%b was expected\x1b[m", N, op_in, flags_out, Y_out, flags_exp[N], Y_exp[N]);
+                error_count = error_count + 1;
+            end
+        end
+
+        if (error_count == 0) $display("\x1b[38;5;10mAll ALU tests passing\x1b[m");
+        else $display("\x1b[38;5;9m%0d ALU test(s) failing\x1b[m", error_count);
+    end
+endmodule

ModelSim/asu.sv

@@ -0,0 +1,22 @@
+`ifndef ASU_H_SV
+`define ASU_H_SV
+
+module asu #(parameter width = 2)(
+	input logic [0:0] op,
+	input logic[2**width-1:0] A, input logic[2**width-1:0] B,
+   output logic[2**width-1:0] OUT_1, output logic[0:0] COUT, output logic[0:0] OUT_CIN);
+
+    logic [2**width-1:0] operand;
+    always_comb begin
+        // A + (sub) ? B : -B
+        // Adds an extra bit to all operands to calculate the carry bit. Not optimal for hardware synthesis
+        //operand = (B ^ {(2**width){op}});
+        operand = op == 1'b0 ? B : ~B;
+        {COUT, OUT_1} = A + operand + {{(2**width-1){1'b0}}, op};
+    end
+
+    // Need to do this outside of the always_comb block because parameter-based bitslicing/indexing isn't supported?
+    // Cin for final bit in adder to later be xor'ed with COUT to determine if a signed overflow occured for the MIPS architecture
+    assign OUT_CIN = A[2**width-1] ^ operand[2**width-1] ^ OUT_1[2**width-1];
+endmodule
+`endif

ModelSim/asu_tb.sv

@@ -0,0 +1,122 @@
+`include "asu.sv"
+
+module asu_tb #(width=4)();
+    logic [0:0] op;
+    logic [width-1:0] A;
+    logic [width-1:0] B;
+    logic [width-1:0] C;
+    logic [0:0] Cout;
+    logic [0:0] Cin;
+    logic [width-1:0] C_exp;
+    logic [0:0] Cout_exp;
+    logic [0:0] Cin_exp;   // TODO
+
+    asu #($clog2(width)) dut(op, A, B, C, Cout, Cin);
+
+    integer error_count;
+    initial begin
+        error_count = 0;
+        $display("Beginning ASU tests");
+
+        // Test basic addition of 0+1 = 1
+        op = 1'b0;
+        A = {width{1'b0}};
+        B = { {(width-1){1'b0}}, 1'b1};
+        C_exp = { {(width-1){1'b0}}, 1'b1};
+        Cout_exp = 1'b0;
+        Cin_exp = 1'b0;
+        #1;
+        if (C != C_exp || Cout != Cout_exp || Cin != Cin_exp || (Cin ^ Cout) != (Cin_exp ^ Cout_exp)) begin
+            $display("\t\x1b[38;5;9mOp 0b%b(0b%b, 0b%b) produced 0b%b%b_%b but 0b%b%b_%b was expected\x1b[m", op, A, B, Cin, Cout, C, Cin_exp, Cout_exp, C_exp);
+            error_count = error_count + 1;
+        end
+
+        // Test underflow from 0-1 = UINTMAX
+        op = 1'b1;
+        C_exp = {(width){1'b1}};
+        Cout_exp = 1'b0;
+        Cin_exp = 1'b0;
+        #1;
+        if (C != C_exp || Cout != Cout_exp || Cin != Cin_exp || (Cin ^ Cout) != (Cin_exp ^ Cout_exp)) begin
+            $display("\t\x1b[38;5;9mOp 0b%b(0b%b, 0b%b) produced 0b%b%b_%b but 0b%b%b_%b was expected\x1b[m", op, A, B, Cin, Cout, C, Cin_exp, Cout_exp, C_exp);
+            error_count = error_count + 1;
+        end
+
+        // Test carry addition of 1+1 = 2
+        op = 1'b0;
+        A = { {(width-1){1'b0}}, 1'b1};
+        B = { {(width-1){1'b0}}, 1'b1};
+        C_exp = { {(width-2){1'b0}}, 2'b10};
+        Cout_exp = 1'b0;
+        Cin_exp = 1'b0;
+        #1;
+        if (C != C_exp || Cout != Cout_exp || Cin != Cin_exp || (Cin ^ Cout) != (Cin_exp ^ Cout_exp)) begin
+            $display("\t\x1b[38;5;9mOp 0b%b(0b%b, 0b%b) produced 0b%b%b_%b but 0b%b%b_%b was expected\x1b[m", op, A, B, Cin, Cout, C, Cin_exp, Cout_exp, C_exp);
+            error_count = error_count + 1;
+        end
+
+        // Test overflow from  UINTMAX+1 = 0
+        A = {(width){1'b1}};            // UINTMAX
+        B = { {(width-1){1'b0}}, 1'b1}; // 1
+        C_exp = {(width){1'b0}};
+        Cout_exp = 1'b1;
+        Cin_exp = 1'b1;
+        #1;
+        if (C != C_exp || Cout != Cout_exp || Cin != Cin_exp || (Cin ^ Cout) != (Cin_exp ^ Cout_exp)) begin
+            $display("\t\x1b[38;5;9mOp 0b%b(0b%b, 0b%b) produced 0b%b%b_%b but 0b%b%b_%b was expected\x1b[m", op, A, B, Cin, Cout, C, Cin_exp, Cout_exp, C_exp);
+            error_count = error_count + 1;
+        end
+
+        // Tests INTMAX+1
+        op = 1'b0;
+        A = {1'b0, {(width-1){1'b1}}};          // INTMAX
+        B = {{(width-1){1'b0}}, 1'b1};          // 1
+        C_exp    = {1'b1, {(width-1){1'b0}}};   // -INTMAX
+        Cin_exp  = 1'b1;
+        Cout_exp = 1'b0;
+        #1;
+        if (C != C_exp || Cout != Cout_exp || Cin != Cin_exp || (Cin ^ Cout) != (Cin_exp ^ Cout_exp)) begin
+            $display("\t\x1b[38;5;9mOp 0b%b(0b%b, 0b%b) produced 0b%b%b_%b but 0b%b%b_%b was expected\x1b[m", op, A, B, Cin, Cout, C, Cin_exp, Cout_exp, C_exp);
+            error_count = error_count + 1;
+        end
+
+        op = 1'b0;
+        A = {1'b1, {(width-1){1'b0}}};  // -INTMAX
+        B = {1'b1, {(width-1){1'b0}}};  // -INTMAX
+        C_exp    = {width{1'b0}};       // 0
+        Cin_exp  = 1'b0;
+        Cout_exp = 1'b1;
+        #1;
+        if (C != C_exp || Cout != Cout_exp || Cin != Cin_exp || (Cin ^ Cout) != (Cin_exp ^ Cout_exp)) begin
+            $display("\t\x1b[38;5;9mOp 0b%b(0b%b, 0b%b) produced 0b%b%b_%b but 0b%b%b_%b was expected\x1b[m", op, A, B, Cin, Cout, C, Cin_exp, Cout_exp, C_exp);
+            error_count = error_count + 1;
+        end
+
+        op = 1'b1;
+        A = {1'b0, {(width-1){1'b1}}}; // INTMAX
+        B = {1'b1, {(width-1){1'b0}}}; // -INTMAX
+        C_exp    = {width{1'b1}};      // -1
+        Cin_exp  = 1'b1;
+        Cout_exp = 1'b0;
+        #1;
+        if (C != C_exp || Cout != Cout_exp || Cin != Cin_exp || (Cin ^ Cout) != (Cin_exp ^ Cout_exp)) begin
+            $display("\t\x1b[38;5;9mOp 0b%b(0b%b, 0b%b) produced 0b%b%b_%b but 0b%b%b_%b was expected\x1b[m", op, A, B, Cin, Cout, C, Cin_exp, Cout_exp, C_exp);
+            error_count = error_count + 1;
+        end
+
+        op = 1'b1;
+        A = {1'b1, {(width-1){1'b0}}};          // -INTMAX
+        B = {{(width-1){1'b0}}, 1'b1};          // 1
+        C_exp    = {1'b0, {(width-1){1'b1}}};   // INTMAX
+        Cin_exp  = 1'b0;
+        Cout_exp = 1'b1;
+        #1;
+        if (C != C_exp || Cout != Cout_exp || Cin != Cin_exp || (Cin ^ Cout) != (Cin_exp ^ Cout_exp)) begin
+            $display("\t\x1b[38;5;9mOp 0b%b(0b%b, 0b%b) produced 0b%b%b_%b but 0b%b%b_%b was expected\x1b[m", op, A, B, Cin, Cout, C, Cin_exp, Cout_exp, C_exp);
+            error_count = error_count + 1;
+        end
+
+        if (error_count == 0) $display("\x1b[38;5;10mAll ASU tests passing\x1b[m");
+        else $display("\x1b[38;5;9m%0d ASU test(s) failing\x1b[m", error_count);
+    end
+endmodule

ModelSim/asu_tb.sv.bak

@@ -0,0 +1,122 @@
+`include "asu.sv"
+
+module asu_tb #(width=8)();
+    logic [0:0] op;
+    logic [width-1:0] A;
+    logic [width-1:0] B;
+    logic [width-1:0] C;
+    logic [0:0] Cout;
+    logic [0:0] Cin;
+    logic [width-1:0] C_exp;
+    logic [0:0] Cout_exp;
+    logic [0:0] Cin_exp;   // TODO
+
+    asu #($clog2(width)) dut(op, A, B, C, Cout, Cin);
+
+    integer error_count;
+    initial begin
+        error_count = 0;
+        $display("Beginning ASU tests");
+
+        // Test basic addition of 0+1 = 1
+        op = 1'b0;
+        A = {width{1'b0}};
+        B = { {(width-1){1'b0}}, 1'b1};
+        C_exp = { {(width-1){1'b0}}, 1'b1};
+        Cout_exp = 1'b0;
+        Cin_exp = 1'b0;
+        #1;
+        if (C != C_exp || Cout != Cout_exp || Cin != Cin_exp || (Cin ^ Cout) != (Cin_exp ^ Cout_exp)) begin
+            $display("\t\x1b[38;5;9mOp 0b%b(0b%b, 0b%b) produced 0b%b%b_%b but 0b%b%b_%b was expected\x1b[m", op, A, B, Cin, Cout, C, Cin_exp, Cout_exp, C_exp);
+            error_count = error_count + 1;
+        end
+
+        // Test underflow from 0-1 = UINTMAX
+        op = 1'b1;
+        C_exp = {(width){1'b1}};
+        Cout_exp = 1'b0;
+        Cin_exp = 1'b0;
+        #1;
+        if (C != C_exp || Cout != Cout_exp || Cin != Cin_exp || (Cin ^ Cout) != (Cin_exp ^ Cout_exp)) begin
+            $display("\t\x1b[38;5;9mOp 0b%b(0b%b, 0b%b) produced 0b%b%b_%b but 0b%b%b_%b was expected\x1b[m", op, A, B, Cin, Cout, C, Cin_exp, Cout_exp, C_exp);
+            error_count = error_count + 1;
+        end
+
+        // Test carry addition of 1+1 = 2
+        op = 1'b0;
+        A = { {(width-1){1'b0}}, 1'b1};
+        B = { {(width-1){1'b0}}, 1'b1};
+        C_exp = { {(width-2){1'b0}}, 2'b10};
+        Cout_exp = 1'b0;
+        Cin_exp = 1'b0;
+        #1;
+        if (C != C_exp || Cout != Cout_exp || Cin != Cin_exp || (Cin ^ Cout) != (Cin_exp ^ Cout_exp)) begin
+            $display("\t\x1b[38;5;9mOp 0b%b(0b%b, 0b%b) produced 0b%b%b_%b but 0b%b%b_%b was expected\x1b[m", op, A, B, Cin, Cout, C, Cin_exp, Cout_exp, C_exp);
+            error_count = error_count + 1;
+        end
+
+        // Test overflow from  UINTMAX+1 = 0
+        A = {(width){1'b1}};            // UINTMAX
+        B = { {(width-1){1'b0}}, 1'b1}; // 1
+        C_exp = {(width){1'b0}};
+        Cout_exp = 1'b1;
+        Cin_exp = 1'b1;
+        #1;
+        if (C != C_exp || Cout != Cout_exp || Cin != Cin_exp || (Cin ^ Cout) != (Cin_exp ^ Cout_exp)) begin
+            $display("\t\x1b[38;5;9mOp 0b%b(0b%b, 0b%b) produced 0b%b%b_%b but 0b%b%b_%b was expected\x1b[m", op, A, B, Cin, Cout, C, Cin_exp, Cout_exp, C_exp);
+            error_count = error_count + 1;
+        end
+
+        // Tests INTMAX+1
+        op = 1'b0;
+        A = {1'b0, {(width-1){1'b1}}};          // INTMAX
+        B = {{(width-1){1'b0}}, 1'b1};          // 1
+        C_exp    = {1'b1, {(width-1){1'b0}}};   // -INTMAX
+        Cin_exp  = 1'b1;
+        Cout_exp = 1'b0;
+        #1;
+        if (C != C_exp || Cout != Cout_exp || Cin != Cin_exp || (Cin ^ Cout) != (Cin_exp ^ Cout_exp)) begin
+            $display("\t\x1b[38;5;9mOp 0b%b(0b%b, 0b%b) produced 0b%b%b_%b but 0b%b%b_%b was expected\x1b[m", op, A, B, Cin, Cout, C, Cin_exp, Cout_exp, C_exp);
+            error_count = error_count + 1;
+        end
+
+        op = 1'b0;
+        A = {1'b1, {(width-1){1'b0}}};  // -INTMAX
+        B = {1'b1, {(width-1){1'b0}}};  // -INTMAX
+        C_exp    = {width{1'b0}};       // 0
+        Cin_exp  = 1'b0;
+        Cout_exp = 1'b1;
+        #1;
+        if (C != C_exp || Cout != Cout_exp || Cin != Cin_exp || (Cin ^ Cout) != (Cin_exp ^ Cout_exp)) begin
+            $display("\t\x1b[38;5;9mOp 0b%b(0b%b, 0b%b) produced 0b%b%b_%b but 0b%b%b_%b was expected\x1b[m", op, A, B, Cin, Cout, C, Cin_exp, Cout_exp, C_exp);
+            error_count = error_count + 1;
+        end
+
+        op = 1'b1;
+        A = {1'b0, {(width-1){1'b1}}}; // INTMAX
+        B = {1'b1, {(width-1){1'b0}}}; // -INTMAX
+        C_exp    = {width{1'b1}};      // -1
+        Cin_exp  = 1'b1;
+        Cout_exp = 1'b0;
+        #1;
+        if (C != C_exp || Cout != Cout_exp || Cin != Cin_exp || (Cin ^ Cout) != (Cin_exp ^ Cout_exp)) begin
+            $display("\t\x1b[38;5;9mOp 0b%b(0b%b, 0b%b) produced 0b%b%b_%b but 0b%b%b_%b was expected\x1b[m", op, A, B, Cin, Cout, C, Cin_exp, Cout_exp, C_exp);
+            error_count = error_count + 1;
+        end
+
+        op = 1'b1;
+        A = {1'b1, {(width-1){1'b0}}};          // -INTMAX
+        B = {{(width-1){1'b0}}, 1'b1};          // 1
+        C_exp    = {1'b0, {(width-1){1'b1}}};   // INTMAX
+        Cin_exp  = 1'b0;
+        Cout_exp = 1'b1;
+        #1;
+        if (C != C_exp || Cout != Cout_exp || Cin != Cin_exp || (Cin ^ Cout) != (Cin_exp ^ Cout_exp)) begin
+            $display("\t\x1b[38;5;9mOp 0b%b(0b%b, 0b%b) produced 0b%b%b_%b but 0b%b%b_%b was expected\x1b[m", op, A, B, Cin, Cout, C, Cin_exp, Cout_exp, C_exp);
+            error_count = error_count + 1;
+        end
+
+        if (error_count == 0) $display("\x1b[38;5;10mAll ASU tests passing\x1b[m");
+        else $display("\x1b[38;5;9m%0d ASU test(s) failing\x1b[m", error_count);
+    end
+endmodule

ModelSim/instruction_classifier.sv

@@ -0,0 +1,21 @@
+`ifndef INSTRUCTION_CLASSIFIER_H_SV
+`define INSTRUCTION_CLASSIFIER_H_SV
+module instruction_classifier(input logic[5:0] op,
+    output logic[0:0] R, output logic[0:0] B1, output logic[0:0] J,
+    output logic[0:0] B2, output logic[0:0] I, output logic[0:0] F,
+    output logic[0:0] M);
+
+    always_comb begin
+        // Performs a rolling equals check
+        //  Uses an AND mask to mask off bits we don't care about
+        //  And a equals operator to perform a bitwise XNOR followed by a horizontal AND 
+        R = ( (op & 6'b111111) == 6'b000000);
+        B1= ( (op & 6'b111111) == 6'b000001);
+        J = ( (op & 6'b111110) == 6'b000010);
+        B2= ( (op & 6'b111100) == 6'b000100);
+        I = ( (op & 6'b111000) == 6'b001000);
+        F = ( (op & 6'b110000) == 6'b010000);
+        M = ( (op & 6'b100000) == 6'b100000);
+    end
+endmodule
+`endif

ModelSim/instruction_classifier_tb.sv

@@ -0,0 +1,52 @@
+`include "instruction_classifier.sv"
+module instruction_classifier_tb();
+    logic [5:0] op;
+    logic [6:0] C;
+    logic [5:0] ops[12];
+    logic [6:0] C_exp[12];
+
+    instruction_classifier dut(op, C[0:0], C[1:1], C[2:2], C[3:3], C[4:4], C[5:5], C[6:6]);
+
+    integer error_count;
+    initial begin
+        ops[0] = 6'b000000;
+        C_exp[0] = 7'b0000001;
+        ops[1] = 6'b000001;
+        C_exp[1] = 7'b0000010;
+        ops[2] = 6'b000010;
+        C_exp[2] = 7'b0000100;
+        ops[3] = 6'b000100;
+        C_exp[3] = 7'b0001000;
+        ops[4] = 6'b001000;
+        C_exp[4] = 7'b0010000;
+        ops[5] = 6'b010000;
+        C_exp[5] = 7'b0100000;
+        ops[6] = 6'b100000;
+        C_exp[6] = 7'b1000000;
+
+        ops[7] = 6'b000011;
+        C_exp[7] = 7'b0000100;
+        ops[8] = 6'b000101;
+        C_exp[8] = 7'b0001000;
+        ops[9] = 6'b001001;
+        C_exp[9] = 7'b0010000;
+        ops[10] = 6'b010001;
+        C_exp[10] = 7'b0100000;
+        ops[11] = 6'b100001;
+        C_exp[11] = 7'b1000000;
+
+        error_count = 0;
+        $display("Beginning Instruction Classifier tests");
+        for (integer N = 0; N < $size(ops); ++N) begin
+            op = ops[N];
+            #1;
+            if (C != C_exp[N]) begin
+                $display("\t\x1b[38;5;9mInstruction 0b%b produced 0b%b but 0b%b was expected\x1b[m", op, C, C_exp[N]);
+                error_count = error_count + 1;
+            end
+        end
+        if (error_count == 0) $display("\x1b[38;5;10mAll Instruction Classifier tests passing\x1b[m");
+        else $display("\x1b[38;5;9m%0d Instruction Classifier test(s) failing\x1b[m", error_count);
+    end
+
+endmodule

ModelSim/lu.sv

@@ -1,3 +1,5 @@
+`ifndef LU_H_SV
+`define LU_H_SV
 module lu #(parameter width = 2) (
     input logic [1:0] op,
     input logic [2**width-1:0] A,
@@ -14,3 +16,4 @@ module lu #(parameter width = 2) (
 		endcase
     end
 endmodule
+`endif

ModelSim/lu_tb.sv

@@ -1,36 +1,36 @@
 `include "lu.sv"
 
-module lu_tb #(W=4)();
+module lu_tb #(parameter W=4)();
     logic [1:0] op;
     logic [W-1:0] A;
     logic [W-1:0] B;
     logic [W-1:0] C;
     logic [W-1:0] C_exp[16];
 
-    lu #(W) dut();
+    lu #(W/2) dut(op, A, B, C);
 
     integer error_count;
     initial begin
         // AND
-        C_exp[0]  = {W{1'b0}};
-        C_exp[1]  = {W{1'b0}};
-        C_exp[2]  = {W{1'b0}};
-        C_exp[3]  = {W{1'b0}};
+        C_exp[0]  = {{W{1'b0}}, {1'b0}};
+        C_exp[1]  = {{W{1'b0}}, {1'b0}};
+        C_exp[2]  = {{W{1'b0}}, {1'b0}};
+        C_exp[3]  = {{W{1'b0}}, {1'b1}};
         // OR
-        C_exp[4]  = {W{1'b0}};
-        C_exp[5]  = {W{1'b1}};
-        C_exp[6]  = {W{1'b1}};
-        C_exp[7]  = {W{1'b1}};
+        C_exp[4]  = {{W{1'b0}}, {1'b0}};
+        C_exp[5]  = {{W{1'b0}}, {1'b1}};
+        C_exp[6]  = {{W{1'b0}}, {1'b1}};
+        C_exp[7]  = {{W{1'b0}}, {1'b1}};
         // XOR
-        C_exp[8]  = {W{1'b0}};
-        C_exp[9]  = {W{1'b1}};
-        C_exp[10] = {W{1'b1}};
-        C_exp[11] = {W{1'b0}};
+        C_exp[8]  = {{W{1'b0}}, {1'b0}};
+        C_exp[9]  = {{W{1'b0}}, {1'b1}};
+        C_exp[10] = {{W{1'b0}}, {1'b1}};
+        C_exp[11] = {{W{1'b0}}, {1'b0}};
         // NOR
-        C_exp[12] = {W{1'b1}};
-        C_exp[13] = {W{1'b0}};
-        C_exp[14] = {W{1'b0}};
-        C_exp[15] = {W{1'b0}};
+        C_exp[12] = {{W{1'b1}}, {1'b1}};
+        C_exp[13] = {{W{1'b1}}, {1'b0}};
+        C_exp[14] = {{W{1'b1}}, {1'b0}};
+        C_exp[15] = {{W{1'b1}}, {1'b0}};
 
         error_count = 0;
         op = 0;
@@ -42,12 +42,13 @@ module lu_tb #(W=4)();
                 for (integer K = 0; K < 2; ++K) begin
                     #1;
                     if (C != C_exp[N*2*2 + M*2 + K]) begin
-                        $display("\t\x1b[38;5;9mOp 0b%b(0b%b, 0b%b) produced 0b%b but 0b%b was expected\x1b[m", op, A, B, C, C_exp[N*2*2 + M*2 + K]);
+                        $display("\t\x1b[38;5;9mLU(%0d) Op 0b%b(0b%b, 0b%b) produced 0b%b but 0b%b was expected\x1b[m", N*2*2+M*2+K, op, A, B, C, C_exp[N*2*2 + M*2 + K]);
                         error_count = error_count + 1;
                     end
                     B = 1;
                 end
                 A = 1;
+                B = 0;
             end
             A = 0;
             B = 0;

ModelSim/seven_seg.sv

@@ -0,0 +1,26 @@
+`ifndef SEVEN_SEG_H_SV
+`define SEVEN_SEG_H_SV
+module seven_seg(input logic [3:0] num, input logic [0:0] rbi_inv, output logic [7:0] segments);
+        always_comb begin
+           case (num)
+               4'b0000: segments = (rbi_inv) ? ~(8'b01111111) : ~(8'b00000000);
+               4'b0001: segments = ~(8'b00001101);
+               4'b0010: segments = ~(8'b10110111);
+               4'b0011: segments = ~(8'b10011111);
+               4'b0100: segments = ~(8'b11001101);
+               4'b0101: segments = ~(8'b11011011);
+               4'b0110: segments = ~(8'b11111011);
+               4'b0111: segments = ~(8'b00001111);
+               4'b1000: segments = ~(8'b11111111);
+               4'b1001: segments = ~(8'b11001111);
+               4'b1010: segments = ~(8'b11101111);
+               4'b1011: segments = ~(8'b11111001);
+               4'b1100: segments = ~(8'b01110011);
+               4'b1101: segments = ~(8'b10111101);
+               4'b1110: segments = ~(8'b11110011);
+               4'b1111: segments = ~(8'b11100011);
+               default: segments = ~(8'bxxxxxxxx);
+           endcase     
+        end
+endmodule
+`endif

ModelSim/seven_seg_tb.sv

@@ -0,0 +1,68 @@
+`include "seven_seg.sv"
+
+module seven_seg_tb();
+    logic [3:0] in_num;
+    logic [0:0] in_rbi_inv;
+    logic [7:0] out_segments;
+    logic [7:0] true_segments[17];
+
+    seven_seg dut(in_num, in_rbi_inv, out_segments);
+
+    integer N;
+    integer i;
+    integer error_count;
+    initial begin
+
+        // Initialise truth table
+        true_segments[0 ] = ~(8'b01111111);
+        true_segments[1 ] = ~(8'b00001101);
+        true_segments[2 ] = ~(8'b10110111);
+        true_segments[3 ] = ~(8'b10011111);
+        true_segments[4 ] = ~(8'b11001101);
+        true_segments[5 ] = ~(8'b11011011);
+        true_segments[6 ] = ~(8'b11111011);
+        true_segments[7 ] = ~(8'b00001111);
+        true_segments[8 ] = ~(8'b11111111);
+        true_segments[9 ] = ~(8'b11001111);
+        true_segments[10] = ~(8'b11101111);
+        true_segments[11] = ~(8'b11111001);
+        true_segments[12] = ~(8'b01110011);
+        true_segments[13] = ~(8'b10111101);
+        true_segments[14] = ~(8'b11110011);
+        true_segments[15] = ~(8'b11100011);
+        true_segments[16] = ~(8'b00000000); // Special case for RBI
+        
+        $display("Beginning seven-segment tests");
+
+        in_num = 4'd0;
+        in_rbi_inv = 1'b0;
+        error_count = 0;
+        #1;
+        if (out_segments !== true_segments[16]) begin
+            $display("\t\x1b[38;5;9mNumber 0b%b failed to decode to 0b%b, producing 0b%b\x1b[m", in_num, true_segments[16], out_segments);
+            error_count = error_count + 1;
+        end
+        for (N=1; N < 15; ++N) begin
+            in_num = in_num + 1;
+            #1;
+            if (out_segments !== true_segments[N]) begin
+                $display("\t\x1b[38;5;9mNumber 0b%b failed to decode to 0b%b, producing 0b%b\x1b[m", in_num, true_segments[N], out_segments);
+                error_count = error_count + 1;
+            end
+        end
+
+        in_num = 4'd0;
+        in_rbi_inv = 1'b1;
+        for (N=0; N < 15; ++N) begin
+            #1;
+            if (out_segments !== true_segments[N]) begin
+                $display("\t\x1b[38;5;9mNumber 0b%b failed to decode to 0b%b, producing 0b%b\x1b[m", in_num, true_segments[N], out_segments);
+                error_count = error_count + 1;
+            end
+            in_num = in_num + 1;
+        end
+
+        if (error_count == 0) $display("\x1b[38;5;10mAll seven-segment tests passing\x1b[m");
+        else $display("\x1b[38;5;9m%0d seven-segment test(s) failing\x1b[m", error_count);
+    end
+endmodule

ModelSim/shifter.sv

@@ -0,0 +1,19 @@
+`ifndef SHIFTER_H_SV
+`define SHIFTER_H_SV
+module shifter #(width=2)(input logic [2:0] op,
+    input logic[2**width-1:0] A, input logic[2**width-1:0] B, input logic[width-1:0] C,
+    output logic[2**width-1:0] OUT_1);
+
+    always_comb begin
+        case (op)
+            3'b000: OUT_1 = A << C;
+            3'b001: OUT_1 = A >> C;
+            3'b011: OUT_1 = $signed(A) >>> C;
+            3'b100: OUT_1 = A << B;
+            3'b101: OUT_1 = A >> B;
+            3'b111: OUT_1 = $signed(A) >>> B;
+            default:OUT_1 = A;
+        endcase
+    end    
+endmodule
+`endif

ModelSim/shifter_tb.sv

@@ -0,0 +1,77 @@
+`include "shifter.sv"
+module shifter_tb #(width=4)();
+    logic [2:0] op;
+    logic [2**width-1:0] Y;
+    logic [2**width-1:0] A_in;
+    logic [2**width-1:0] B_in;
+    logic [width-1:0] C_in;
+
+    logic [2:0] ops[6];
+    logic [2**width-1:0] A[6];
+    logic [2**width-1:0] B[6];
+    logic [width-1:0] C[6];
+    logic [2**width-1:0] Y_exp[6];
+
+    shifter #(width) dut(op, A_in,B_in,C_in,Y);
+
+    integer error_count;
+    initial begin
+        // Test left shift by C
+        ops[0] = 3'b000;
+        A[0] = {{(2**width-1){1'b0}}, {1'b1}};
+        C[0] = {{(width-1){1'b0}}, {1'b1}};
+        B[0] = {2**width{1'b0}};
+        Y_exp[0] = {{(2**width-2){1'b0}}, {2'b10}};
+
+        // Test left shift by B
+        ops[1] = 3'b100;
+        A[1] = {{(2**width-1){1'b0}}, {1'b1}};
+        C[1] = {{(width-1){1'b0}}, {1'b1}};
+        B[1] = {{(2**width-2){1'b0}}, 2'b10};
+        Y_exp[1] = {{(2**width-3){1'b0}}, {3'b100}};
+
+        // Test Logical right shift by C
+        ops[2] = 3'b001;
+        A[2] = {{(2**width-2){1'b0}}, {2'b10}};
+        C[2] = {{(width-1){1'b0}}, {1'b1}};
+        B[2] = {2**width{1'b0}};
+        Y_exp[2] = {{(2**width-1){1'b0}}, {1'b1}};
+
+        // Test Logical right shift by B
+        ops[3] = 3'b101;
+        A[3] = {{(2**width-1){1'b0}}, {2'b10}};
+        C[3] = {{(width-1){1'b0}}, {1'b1}};
+        B[3] = {{(2**width-2){1'b0}}, 2'b10};
+        Y_exp[3] = {{(2**width-1){1'b0}}, {1'b0}};
+
+        // Test arithmetic shift right by C
+        ops[4] = 3'b011;
+        A[4] = {{(2**width-1){1'b1}}, 1'b0};   // -2
+        C[4] = {{(width-1){1'b0}}, 1'b1};   // 1
+        B[4] = {{(2**width-2){1'b0}}, 2'b10};  // 2
+        Y_exp[4] = {2**width{1'b1}};           // -1
+
+        // Test arithmetic shift right by B
+        ops[5] = 3'b111;
+        A[5] = {{(2**width-2){1'b1}}, 2'b00};   // -4
+        C[5] = {{(width-1){1'b0}}, 1'b1};   // 1
+        B[5] = {{(2**width-2){1'b0}}, 2'b10};  // 2
+        Y_exp[5] = {2**width{1'b1}};           // -1
+
+        error_count = 0;
+        $display("Beginning Shifter tests");
+        for (integer N = 0; N < $size(ops); ++N) begin
+            op = ops[N];
+            A_in = A[N];
+            B_in = B[N];
+            C_in = C[N];
+            #1;
+            if (Y != Y_exp[N]) begin
+                $display("\t\x1b[38;5;9mShifter(%0d) Op 0b%b(0b%b, 0b%b, 0b%b) produced 0b%b but 0b%b was expected\x1b[m", N, op, A_in, B_in, C_in, Y, Y_exp[N]);
+                error_count = error_count + 1;
+            end
+        end
+        if (error_count == 0) $display("\x1b[38;5;10mAll Shifter tests passing\x1b[m");
+        else $display("\x1b[38;5;9m%0d Shifter test(s) failing\x1b[m", error_count);
+    end
+endmodule

ModelSim/tests.sv

@@ -0,0 +1,6 @@
+`include "tests/seven_seg_tb.sv"
+`include "tests/lu_tb.sv"
+`include "tests/asu_tb.sv"
+`include "tests/instruction_classifier_tb.sv"
+`include "tests/shifter_tb.sv"
+`include "tests/alu_tb.sv"

ModelSim/transcript

@@ -1,46 +1,21 @@
 # Loading project Assignment_1_Q2
-# Compile of lu.sv was successful.
-# Compile of lu_tb.sv failed with 1 errors.
-# 2 compiles, 1 failed with 1 error.
-# Compile of lu_tb.sv failed with 1 errors.
-# Compile of lu.sv was successful.
-# Compile of lu_tb.sv was successful.
-# 2 compiles, 0 failed with no errors.
 vsim work.lu_tb
 # vsim work.lu_tb 
-# Start time: 16:26:37 on Sep 08,2026
+# Start time: 16:47:26 on Sep 15,2026
 # Loading sv_std.std
 # Loading work.lu_tb
 # Loading work.lu
-# ** Warning: (vsim-2685) [TFMPC] - Too few port connections for 'dut'.  Expected 4, found 0.
-#    Time: 0 ps  Iteration: 0  Instance: /lu_tb/dut File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/lu_tb.sv Line: 10
-# ** Warning: (vsim-3722) /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/lu_tb.sv(10): [TFMPC] - Missing connection for port 'op'.
-# ** Warning: (vsim-3722) /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/lu_tb.sv(10): [TFMPC] - Missing connection for port 'A'.
-# ** Warning: (vsim-3722) /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/lu_tb.sv(10): [TFMPC] - Missing connection for port 'B'.
-# ** Warning: (vsim-3722) /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/lu_tb.sv(10): [TFMPC] - Missing connection for port 'Y'.
 add wave -position end  sim:/lu_tb/op
 add wave -position end  sim:/lu_tb/A
-add wave -position end  sim:/lu_tb/A
 add wave -position end  sim:/lu_tb/B
 add wave -position end  sim:/lu_tb/C
-quit -sim
-# End time: 16:28:07 on Sep 08,2026, Elapsed time: 0:01:30
-# Errors: 0, Warnings: 12
-# Compile of lu.sv was successful.
-# Compile of lu_tb.sv was successful.
-# 2 compiles, 0 failed with no errors.
-vsim work.lu_tb
-# vsim work.lu_tb 
-# Start time: 16:30:51 on Sep 08,2026
-# Loading sv_std.std
-# Loading work.lu_tb
-# Loading work.lu
-# ** Warning: (vsim-2685) [TFMPC] - Too few port connections for 'dut'.  Expected 4, found 0.
-#    Time: 0 ps  Iteration: 0  Instance: /lu_tb/dut File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/lu_tb.sv Line: 10
-# ** Warning: (vsim-3722) /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/lu_tb.sv(10): [TFMPC] - Missing connection for port 'op'.
-# ** Warning: (vsim-3722) /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/lu_tb.sv(10): [TFMPC] - Missing connection for port 'A'.
-# ** Warning: (vsim-3722) /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/lu_tb.sv(10): [TFMPC] - Missing connection for port 'B'.
-# ** Warning: (vsim-3722) /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/lu_tb.sv(10): [TFMPC] - Missing connection for port 'Y'.
-quit -sim
-# End time: 16:31:17 on Sep 08,2026, Elapsed time: 0:00:26
-# Errors: 0, Warnings: 7
+add wave -position end  sim:/lu_tb/C_exp
+run
+# Beginning LU tests
+run
+run
+run
+run -all
+# All LU tests passing
+# End time: 16:52:34 on Sep 15,2026, Elapsed time: 0:05:08
+# Errors: 0, Warnings: 1

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Quartus/A1_Q1/db/prev_cmp_q1.qmsg

@@ -1,135 +1,139 @@
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1788418238472 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1788418238472 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Sep  3 16:50:38 2026 " "Processing started: Thu Sep  3 16:50:38 2026" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1788418238472 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1788418238472 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off q1 -c seven_seg " "Command: quartus_map --read_settings_files=on --write_settings_files=off q1 -c seven_seg" {  } {  } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1788418238473 ""}
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1788418238798 ""}
-{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1788418238799 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "seven_seg.sv 1 1 " "Found 1 design units, including 1 entities, in source file seven_seg.sv" { { "Info" "ISGN_ENTITY_NAME" "1 seven_seg " "Found entity 1: seven_seg" {  } { { "seven_seg.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q1/seven_seg.sv" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1788418248175 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1788418248175 ""}
-{ "Info" "ISGN_START_ELABORATION_TOP" "seven_seg " "Elaborating entity \"seven_seg\" for the top level hierarchy" {  } {  } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1788418248310 ""}
-{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" {  } {  } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1788418248991 ""}
-{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" {  } {  } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1788418249329 ""}  } {  } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1788418249329 ""}
-{ "Info" "ICUT_CUT_TM_SUMMARY" "21 " "Implemented 21 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "5 " "Implemented 5 input pins" {  } {  } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1788418249357 ""} { "Info" "ICUT_CUT_TM_OPINS" "8 " "Implemented 8 output pins" {  } {  } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1788418249357 ""} { "Info" "ICUT_CUT_TM_LCELLS" "8 " "Implemented 8 logic cells" {  } {  } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1788418249357 ""}  } {  } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1788418249357 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1  Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "436 " "Peak virtual memory: 436 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1788418249362 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Sep  3 16:50:49 2026 " "Processing ended: Thu Sep  3 16:50:49 2026" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1788418249362 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:11 " "Elapsed time: 00:00:11" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1788418249362 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:25 " "Total CPU time (on all processors): 00:00:25" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1788418249362 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1788418249362 ""}
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Analysis & Synthesis" 0 -1 1788418250890 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus Prime " "Running Quartus Prime Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1788418250891 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Sep  3 16:50:50 2026 " "Processing started: Thu Sep  3 16:50:50 2026" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1788418250891 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Fitter" 0 -1 1788418250891 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off q1 -c seven_seg " "Command: quartus_fit --read_settings_files=off --write_settings_files=off q1 -c seven_seg" {  } {  } 0 0 "Command: %1!s!" 0 0 "Fitter" 0 -1 1788418250891 ""}
-{ "Info" "0" "" "qfit2_default_script.tcl version: #1" {  } {  } 0 0 "qfit2_default_script.tcl version: #1" 0 0 "Fitter" 0 0 1788418250948 ""}
-{ "Info" "0" "" "Project  = q1" {  } {  } 0 0 "Project  = q1" 0 0 "Fitter" 0 0 1788418250949 ""}
-{ "Info" "0" "" "Revision = seven_seg" {  } {  } 0 0 "Revision = seven_seg" 0 0 "Fitter" 0 0 1788418250949 ""}
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1788418251145 ""}
-{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1788418251145 ""}
-{ "Info" "IMPP_MPP_USER_DEVICE" "seven_seg 5CGXFC5C6F27C7 " "Selected device 5CGXFC5C6F27C7 for design \"seven_seg\"" {  } {  } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1788418251150 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1788418251234 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1788418251234 ""}
-{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1788418251659 ""}
-{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." {  } {  } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1788418251690 ""}
-{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" {  } {  } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1788418251743 ""}
-{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_START_INFO" "" "Starting Fitter periphery placement operations" {  } {  } 0 184020 "Starting Fitter periphery placement operations" 0 0 "Fitter" 0 -1 1788418258575 ""}
-{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_END_INFO" "00:00:00 " "Fitter periphery placement operations ending: elapsed time is 00:00:00" {  } {  } 0 184021 "Fitter periphery placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1788418258594 ""}
-{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" {  } {  } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1788418258596 ""}
-{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" {  } {  } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1788418258596 ""}
-{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" {  } {  } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1788418258597 ""}
-{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" {  } {  } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1788418258597 ""}
-{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" {  } {  } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1788418258597 ""}
-{ "Extra Info" "IFSAC_FSAC_START_IO_MAC_RAM_PACKING" "" "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" {  } {  } 1 176246 "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1788418258597 ""}
-{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MAC_RAM_PACKING" "" "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" {  } {  } 1 176247 "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1788418258597 ""}
-{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" {  } {  } 1 176219 "No registers were packed into other blocks" 0 0 "Design Software" 0 -1 1788418258598 ""}  } {  } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1788418258598 ""}
-{ "Info" "IFSV_FITTER_PREPARATION_END" "00:00:07 " "Fitter preparation operations ending: elapsed time is 00:00:07" {  } {  } 0 11798 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1788418258614 ""}
-{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "seven_seg.sdc " "Synopsys Design Constraints File file not found: 'seven_seg.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." {  } {  } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1788418264548 ""}
-{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" {  } {  } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1788418264548 ""}
-{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." {  } {  } 0 332096 "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." 0 0 "Fitter" 0 -1 1788418264549 ""}
-{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." {  } {  } 0 332068 "No clocks defined in design." 0 0 "Fitter" 0 -1 1788418264549 ""}
-{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" {  } {  } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1788418264550 ""}
-{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." {  } {  } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Fitter" 0 -1 1788418264550 ""}
-{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." {  } {  } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1788418264550 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" {  } {  } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1788418264553 ""}
-{ "Info" "IVPR20K_VPR_APL_ENABLED" "" "The Fitter is using Advanced Physical Optimization." {  } {  } 0 14951 "The Fitter is using Advanced Physical Optimization." 0 0 "Fitter" 0 -1 1788418264639 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:01 " "Fitter placement preparation operations ending: elapsed time is 00:00:01" {  } {  } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1788418265244 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" {  } {  } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1788418265528 ""}
-{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" {  } {  } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1788418265879 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1788418265879 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" {  } {  } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1788418266738 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X57_Y0 X68_Y11 " "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X57_Y0 to location X68_Y11" {  } { { "loc" "" { Generic "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q1/" { { 1 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X57_Y0 to location X68_Y11"} { { 12 { 0 ""} 57 0 12 12 }  }  }  }  } }  } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1788418272208 ""}  } {  } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1788418272208 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" {  } {  } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1788418272439 ""} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Optimizations that may affect the design's timing were skipped" {  } {  } 0 170200 "Optimizations that may affect the design's timing were skipped" 0 0 "Design Software" 0 -1 1788418272439 ""}  } {  } 0 170199 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1788418272439 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Fitter routing operations ending: elapsed time is 00:00:01" {  } {  } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1788418272442 ""}
-{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.08 " "Total time spent on timing analysis during the Fitter is 0.08 seconds." {  } {  } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1788418273557 ""}
-{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1788418273604 ""}
-{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1788418273960 ""}
-{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1788418273961 ""}
-{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1788418274597 ""}
-{ "Info" "IFSV_FITTER_POST_OPERATION_END" "00:00:04 " "Fitter post-fit operations ending: elapsed time is 00:00:04" {  } {  } 0 11801 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1788418277269 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 5 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "1379 " "Peak virtual memory: 1379 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1788418278082 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Sep  3 16:51:18 2026 " "Processing ended: Thu Sep  3 16:51:18 2026" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1788418278082 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:28 " "Elapsed time: 00:00:28" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1788418278082 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:40 " "Total CPU time (on all processors): 00:00:40" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1788418278082 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1788418278082 ""}
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Fitter" 0 -1 1788418279693 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1788418279694 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Sep  3 16:51:19 2026 " "Processing started: Thu Sep  3 16:51:19 2026" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1788418279694 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1788418279694 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off q1 -c seven_seg " "Command: quartus_asm --read_settings_files=off --write_settings_files=off q1 -c seven_seg" {  } {  } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1788418279694 ""}
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1788418280347 ""}
-{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" {  } {  } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1788418284575 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1  Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "525 " "Peak virtual memory: 525 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1788418284739 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Sep  3 16:51:24 2026 " "Processing ended: Thu Sep  3 16:51:24 2026" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1788418284739 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Elapsed time: 00:00:05" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1788418284739 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Total CPU time (on all processors): 00:00:05" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1788418284739 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1788418284739 ""}
-{ "Info" "IFLOW_DISABLED_MODULE" "Power Analyzer FLOW_ENABLE_POWER_ANALYZER " "Skipped module Power Analyzer due to the assignment FLOW_ENABLE_POWER_ANALYZER" {  } {  } 0 293026 "Skipped module %1!s! due to the assignment %2!s!" 0 0 "Assembler" 0 -1 1788418285414 ""}
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Assembler" 0 -1 1788418286132 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus Prime " "Running Quartus Prime Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1788418286132 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Sep  3 16:51:25 2026 " "Processing started: Thu Sep  3 16:51:25 2026" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1788418286132 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Timing Analyzer" 0 -1 1788418286132 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta q1 -c seven_seg " "Command: quartus_sta q1 -c seven_seg" {  } {  } 0 0 "Command: %1!s!" 0 0 "Timing Analyzer" 0 -1 1788418286133 ""}
-{ "Info" "0" "" "qsta_default_script.tcl version: #1" {  } {  } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Timing Analyzer" 0 0 1788418286190 ""}
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Timing Analyzer" 0 -1 1788418286659 ""}
-{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Timing Analyzer" 0 -1 1788418286659 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1788418286734 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1788418286735 ""}
-{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "seven_seg.sdc " "Synopsys Design Constraints File file not found: 'seven_seg.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." {  } {  } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Timing Analyzer" 0 -1 1788418287305 ""}
-{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" {  } {  } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1788418287305 ""}
-{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." {  } {  } 0 332096 "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1788418287306 ""}
-{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." {  } {  } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1788418287306 ""}
-{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" {  } {  } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Timing Analyzer" 0 -1 1788418287306 ""}
-{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." {  } {  } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1788418287306 ""}
-{ "Info" "0" "" "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" {  } {  } 0 0 "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Timing Analyzer" 0 0 1788418287307 ""}
-{ "Info" "ISTA_NO_CLOCKS_TO_REPORT" "" "No clocks to report" {  } {  } 0 332159 "No clocks to report" 0 0 "Timing Analyzer" 0 -1 1788418287311 ""}
-{ "Info" "0" "" "Analyzing Slow 1100mV 85C Model" {  } {  } 0 0 "Analyzing Slow 1100mV 85C Model" 0 0 "Timing Analyzer" 0 0 1788418287312 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788418287313 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788418287316 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788418287317 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788418287318 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788418287319 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788418287319 ""}
-{ "Info" "0" "" "Analyzing Slow 1100mV 0C Model" {  } {  } 0 0 "Analyzing Slow 1100mV 0C Model" 0 0 "Timing Analyzer" 0 0 1788418287321 ""}
-{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1788418287359 ""}
-{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1788418288432 ""}
-{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" {  } {  } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1788418288531 ""}
-{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." {  } {  } 0 332096 "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1788418288531 ""}
-{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." {  } {  } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1788418288531 ""}
-{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." {  } {  } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1788418288531 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788418288532 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788418288534 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788418288534 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788418288535 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788418288536 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788418288536 ""}
-{ "Info" "0" "" "Analyzing Fast 1100mV 85C Model" {  } {  } 0 0 "Analyzing Fast 1100mV 85C Model" 0 0 "Timing Analyzer" 0 0 1788418288538 ""}
-{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1788418288787 ""}
-{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1788418289393 ""}
-{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" {  } {  } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1788418289431 ""}
-{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." {  } {  } 0 332096 "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1788418289432 ""}
-{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." {  } {  } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1788418289432 ""}
-{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." {  } {  } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1788418289432 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788418289433 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788418289434 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788418289435 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788418289436 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788418289436 ""}
-{ "Info" "0" "" "Analyzing Fast 1100mV 0C Model" {  } {  } 0 0 "Analyzing Fast 1100mV 0C Model" 0 0 "Timing Analyzer" 0 0 1788418289438 ""}
-{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" {  } {  } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1788418289582 ""}
-{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." {  } {  } 0 332096 "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1788418289583 ""}
-{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." {  } {  } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1788418289583 ""}
-{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." {  } {  } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1788418289583 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788418289585 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788418289586 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788418289587 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788418289588 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788418289589 ""}
-{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1788418291002 ""}
-{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1788418291002 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 6 s Quartus Prime " "Quartus Prime Timing Analyzer was successful. 0 errors, 6 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "788 " "Peak virtual memory: 788 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1788418291025 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Sep  3 16:51:31 2026 " "Processing ended: Thu Sep  3 16:51:31 2026" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1788418291025 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Elapsed time: 00:00:06" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1788418291025 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Total CPU time (on all processors): 00:00:05" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1788418291025 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Timing Analyzer" 0 -1 1788418291025 ""}
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Timing Analyzer" 0 -1 1788418292644 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus Prime " "Running Quartus Prime EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1788418292645 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Sep  3 16:51:32 2026 " "Processing started: Thu Sep  3 16:51:32 2026" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1788418292645 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1788418292645 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off q1 -c seven_seg " "Command: quartus_eda --read_settings_files=off --write_settings_files=off q1 -c seven_seg" {  } {  } 0 0 "Command: %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1788418292645 ""}
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "EDA Netlist Writer" 0 -1 1788418293402 ""}
-{ "Info" "IWSC_DONE_HDL_GENERATION" "seven_seg.svo /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q1/simulation/questa/ simulation " "Generated file seven_seg.svo in folder \"/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q1/simulation/questa/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1788418293464 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 1  Quartus Prime " "Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "658 " "Peak virtual memory: 658 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1788418293508 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Sep  3 16:51:33 2026 " "Processing ended: Thu Sep  3 16:51:33 2026" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1788418293508 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1788418293508 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1788418293508 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "EDA Netlist Writer" 0 -1 1788418293508 ""}
-{ "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 14 s " "Quartus Prime Full Compilation was successful. 0 errors, 14 warnings" {  } {  } 0 293000 "Quartus Prime %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "EDA Netlist Writer" 0 -1 1788418294224 ""}
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1789470144496 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1789470144497 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Sep 15 21:02:24 2026 " "Processing started: Tue Sep 15 21:02:24 2026" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1789470144497 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1789470144497 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off q1 -c seven_seg " "Command: quartus_map --read_settings_files=on --write_settings_files=off q1 -c seven_seg" {  } {  } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1789470144497 ""}
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1789470144805 ""}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1789470144805 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "seven_seg.sv 2 2 " "Found 2 design units, including 2 entities, in source file seven_seg.sv" { { "Info" "ISGN_ENTITY_NAME" "1 seven_seg " "Found entity 1: seven_seg" {  } { { "seven_seg.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q1/seven_seg.sv" 4 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1789470154069 ""} { "Info" "ISGN_ENTITY_NAME" "2 seven_seg_2digit " "Found entity 2: seven_seg_2digit" {  } { { "seven_seg.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q1/seven_seg.sv" 32 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1789470154069 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1789470154069 ""}
+{ "Info" "ISGN_START_ELABORATION_TOP" "seven_seg_2digit " "Elaborating entity \"seven_seg_2digit\" for the top level hierarchy" {  } {  } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1789470154206 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "seven_seg seven_seg:left_digit " "Elaborating entity \"seven_seg\" for hierarchy \"seven_seg:left_digit\"" {  } { { "seven_seg.sv" "left_digit" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q1/seven_seg.sv" 45 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1789470154211 ""}
+{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" {  } {  } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1789470154952 ""}
+{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" {  } {  } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1789470155309 ""}  } {  } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1789470155309 ""}
+{ "Info" "ICUT_CUT_TM_SUMMARY" "40 " "Implemented 40 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "8 " "Implemented 8 input pins" {  } {  } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1789470155342 ""} { "Info" "ICUT_CUT_TM_OPINS" "16 " "Implemented 16 output pins" {  } {  } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1789470155342 ""} { "Info" "ICUT_CUT_TM_LCELLS" "16 " "Implemented 16 logic cells" {  } {  } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1789470155342 ""}  } {  } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1789470155342 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1  Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "427 " "Peak virtual memory: 427 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1789470155348 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Sep 15 21:02:35 2026 " "Processing ended: Tue Sep 15 21:02:35 2026" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1789470155348 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:11 " "Elapsed time: 00:00:11" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1789470155348 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:25 " "Total CPU time (on all processors): 00:00:25" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1789470155348 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1789470155348 ""}
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Analysis & Synthesis" 0 -1 1789470156795 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus Prime " "Running Quartus Prime Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1789470156795 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Sep 15 21:02:36 2026 " "Processing started: Tue Sep 15 21:02:36 2026" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1789470156795 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Fitter" 0 -1 1789470156795 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off q1 -c seven_seg " "Command: quartus_fit --read_settings_files=off --write_settings_files=off q1 -c seven_seg" {  } {  } 0 0 "Command: %1!s!" 0 0 "Fitter" 0 -1 1789470156796 ""}
+{ "Info" "0" "" "qfit2_default_script.tcl version: #1" {  } {  } 0 0 "qfit2_default_script.tcl version: #1" 0 0 "Fitter" 0 0 1789470156846 ""}
+{ "Info" "0" "" "Project  = q1" {  } {  } 0 0 "Project  = q1" 0 0 "Fitter" 0 0 1789470156847 ""}
+{ "Info" "0" "" "Revision = seven_seg" {  } {  } 0 0 "Revision = seven_seg" 0 0 "Fitter" 0 0 1789470156847 ""}
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1789470157029 ""}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1789470157030 ""}
+{ "Info" "IMPP_MPP_USER_DEVICE" "seven_seg 5CGXFC5C6F27C7 " "Selected device 5CGXFC5C6F27C7 for design \"seven_seg\"" {  } {  } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1789470157034 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1789470157108 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1789470157108 ""}
+{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1789470157526 ""}
+{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." {  } {  } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1789470157553 ""}
+{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" {  } {  } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1789470157615 ""}
+{ "Critical Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "2 24 " "No exact pin location assignment(s) for 2 pins of 24 total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report." {  } {  } 1 169085 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report." 0 0 "Fitter" 0 -1 1789470157886 ""}
+{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_START_INFO" "" "Starting Fitter periphery placement operations" {  } {  } 0 184020 "Starting Fitter periphery placement operations" 0 0 "Fitter" 0 -1 1789470164478 ""}
+{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_END_INFO" "00:00:00 " "Fitter periphery placement operations ending: elapsed time is 00:00:00" {  } {  } 0 184021 "Fitter periphery placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1789470164536 ""}
+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" {  } {  } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1789470164538 ""}
+{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" {  } {  } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1789470164539 ""}
+{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" {  } {  } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1789470164539 ""}
+{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" {  } {  } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1789470164539 ""}
+{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" {  } {  } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1789470164539 ""}
+{ "Extra Info" "IFSAC_FSAC_START_IO_MAC_RAM_PACKING" "" "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" {  } {  } 1 176246 "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1789470164540 ""}
+{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MAC_RAM_PACKING" "" "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" {  } {  } 1 176247 "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1789470164540 ""}
+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" {  } {  } 1 176219 "No registers were packed into other blocks" 0 0 "Design Software" 0 -1 1789470164540 ""}  } {  } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1789470164540 ""}
+{ "Warning" "WCUT_CUT_UNATTACHED_ASGN" "" "Ignored locations or region assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "rbi\[0\] " "Node \"rbi\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/oliver/altera_lite/25.1std/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/oliver/altera_lite/25.1std/quartus/linux64/Assignment Editor.qase" 1 { { 0 "rbi\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1789470164562 ""}  } {  } 0 15705 "Ignored locations or region assignments to the following nodes" 0 0 "Fitter" 0 -1 1789470164562 ""}
+{ "Info" "IFSV_FITTER_PREPARATION_END" "00:00:07 " "Fitter preparation operations ending: elapsed time is 00:00:07" {  } {  } 0 11798 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1789470164562 ""}
+{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "seven_seg.sdc " "Synopsys Design Constraints File file not found: 'seven_seg.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." {  } {  } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1789470170427 ""}
+{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" {  } {  } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1789470170428 ""}
+{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." {  } {  } 0 332096 "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." 0 0 "Fitter" 0 -1 1789470170428 ""}
+{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." {  } {  } 0 332068 "No clocks defined in design." 0 0 "Fitter" 0 -1 1789470170429 ""}
+{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" {  } {  } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1789470170429 ""}
+{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." {  } {  } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Fitter" 0 -1 1789470170430 ""}
+{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." {  } {  } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1789470170430 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" {  } {  } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1789470170433 ""}
+{ "Info" "IVPR20K_VPR_APL_ENABLED" "" "The Fitter is using Advanced Physical Optimization." {  } {  } 0 14951 "The Fitter is using Advanced Physical Optimization." 0 0 "Fitter" 0 -1 1789470170513 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:01 " "Fitter placement preparation operations ending: elapsed time is 00:00:01" {  } {  } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1789470171201 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" {  } {  } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1789470171924 ""}
+{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" {  } {  } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1789470172228 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1789470172228 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" {  } {  } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1789470173218 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X57_Y0 X68_Y11 " "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X57_Y0 to location X68_Y11" {  } { { "loc" "" { Generic "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q1/" { { 1 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X57_Y0 to location X68_Y11"} { { 12 { 0 ""} 57 0 12 12 }  }  }  }  } }  } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1789470178619 ""}  } {  } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1789470178619 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" {  } {  } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1789470178843 ""} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Optimizations that may affect the design's timing were skipped" {  } {  } 0 170200 "Optimizations that may affect the design's timing were skipped" 0 0 "Design Software" 0 -1 1789470178843 ""}  } {  } 0 170199 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1789470178843 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Fitter routing operations ending: elapsed time is 00:00:01" {  } {  } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1789470178845 ""}
+{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.08 " "Total time spent on timing analysis during the Fitter is 0.08 seconds." {  } {  } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1789470179958 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1789470179994 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1789470180391 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1789470180391 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1789470181168 ""}
+{ "Info" "IFSV_FITTER_POST_OPERATION_END" "00:00:04 " "Fitter post-fit operations ending: elapsed time is 00:00:04" {  } {  } 0 11801 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1789470183999 ""}
+{ "Warning" "WFITCC_FITCC_IGNORED_ASSIGNMENT" "" "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." {  } {  } 0 171167 "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." 0 0 "Fitter" 0 -1 1789470184273 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 9 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 9 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "1391 " "Peak virtual memory: 1391 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1789470184834 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Sep 15 21:03:04 2026 " "Processing ended: Tue Sep 15 21:03:04 2026" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1789470184834 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:28 " "Elapsed time: 00:00:28" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1789470184834 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:40 " "Total CPU time (on all processors): 00:00:40" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1789470184834 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1789470184834 ""}
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Fitter" 0 -1 1789470186459 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1789470186459 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Sep 15 21:03:06 2026 " "Processing started: Tue Sep 15 21:03:06 2026" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1789470186459 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1789470186459 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off q1 -c seven_seg " "Command: quartus_asm --read_settings_files=off --write_settings_files=off q1 -c seven_seg" {  } {  } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1789470186459 ""}
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1789470187123 ""}
+{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" {  } {  } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1789470191389 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1  Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "503 " "Peak virtual memory: 503 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1789470191571 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Sep 15 21:03:11 2026 " "Processing ended: Tue Sep 15 21:03:11 2026" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1789470191571 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Elapsed time: 00:00:05" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1789470191571 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Total CPU time (on all processors): 00:00:05" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1789470191571 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1789470191571 ""}
+{ "Info" "IFLOW_DISABLED_MODULE" "Power Analyzer FLOW_ENABLE_POWER_ANALYZER " "Skipped module Power Analyzer due to the assignment FLOW_ENABLE_POWER_ANALYZER" {  } {  } 0 293026 "Skipped module %1!s! due to the assignment %2!s!" 0 0 "Assembler" 0 -1 1789470192322 ""}
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Assembler" 0 -1 1789470193090 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus Prime " "Running Quartus Prime Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1789470193091 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Sep 15 21:03:12 2026 " "Processing started: Tue Sep 15 21:03:12 2026" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1789470193091 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Timing Analyzer" 0 -1 1789470193091 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta q1 -c seven_seg " "Command: quartus_sta q1 -c seven_seg" {  } {  } 0 0 "Command: %1!s!" 0 0 "Timing Analyzer" 0 -1 1789470193091 ""}
+{ "Info" "0" "" "qsta_default_script.tcl version: #1" {  } {  } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Timing Analyzer" 0 0 1789470193144 ""}
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Timing Analyzer" 0 -1 1789470193614 ""}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Timing Analyzer" 0 -1 1789470193614 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1789470193681 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1789470193681 ""}
+{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "seven_seg.sdc " "Synopsys Design Constraints File file not found: 'seven_seg.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." {  } {  } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Timing Analyzer" 0 -1 1789470194265 ""}
+{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" {  } {  } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1789470194265 ""}
+{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." {  } {  } 0 332096 "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1789470194266 ""}
+{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." {  } {  } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1789470194266 ""}
+{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" {  } {  } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Timing Analyzer" 0 -1 1789470194266 ""}
+{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." {  } {  } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1789470194267 ""}
+{ "Info" "0" "" "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" {  } {  } 0 0 "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Timing Analyzer" 0 0 1789470194267 ""}
+{ "Info" "ISTA_NO_CLOCKS_TO_REPORT" "" "No clocks to report" {  } {  } 0 332159 "No clocks to report" 0 0 "Timing Analyzer" 0 -1 1789470194271 ""}
+{ "Info" "0" "" "Analyzing Slow 1100mV 85C Model" {  } {  } 0 0 "Analyzing Slow 1100mV 85C Model" 0 0 "Timing Analyzer" 0 0 1789470194272 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789470194273 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789470194277 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789470194278 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789470194279 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789470194280 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789470194281 ""}
+{ "Info" "0" "" "Analyzing Slow 1100mV 0C Model" {  } {  } 0 0 "Analyzing Slow 1100mV 0C Model" 0 0 "Timing Analyzer" 0 0 1789470194284 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1789470194329 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1789470195669 ""}
+{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" {  } {  } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1789470195772 ""}
+{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." {  } {  } 0 332096 "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1789470195773 ""}
+{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." {  } {  } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1789470195773 ""}
+{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." {  } {  } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1789470195773 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789470195774 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789470195775 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789470195776 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789470195777 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789470195778 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789470195779 ""}
+{ "Info" "0" "" "Analyzing Fast 1100mV 85C Model" {  } {  } 0 0 "Analyzing Fast 1100mV 85C Model" 0 0 "Timing Analyzer" 0 0 1789470195781 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1789470196052 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1789470196791 ""}
+{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" {  } {  } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1789470196831 ""}
+{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." {  } {  } 0 332096 "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1789470196831 ""}
+{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." {  } {  } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1789470196831 ""}
+{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." {  } {  } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1789470196832 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789470196833 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789470196833 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789470196834 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789470196835 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789470196836 ""}
+{ "Info" "0" "" "Analyzing Fast 1100mV 0C Model" {  } {  } 0 0 "Analyzing Fast 1100mV 0C Model" 0 0 "Timing Analyzer" 0 0 1789470196837 ""}
+{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" {  } {  } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1789470196990 ""}
+{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." {  } {  } 0 332096 "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1789470196991 ""}
+{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." {  } {  } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1789470196991 ""}
+{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." {  } {  } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1789470196991 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789470196992 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789470196993 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789470196994 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789470196995 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789470196996 ""}
+{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1789470198469 ""}
+{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1789470198470 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 6 s Quartus Prime " "Quartus Prime Timing Analyzer was successful. 0 errors, 6 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "789 " "Peak virtual memory: 789 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1789470198502 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Sep 15 21:03:18 2026 " "Processing ended: Tue Sep 15 21:03:18 2026" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1789470198502 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Elapsed time: 00:00:06" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1789470198502 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:06 " "Total CPU time (on all processors): 00:00:06" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1789470198502 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Timing Analyzer" 0 -1 1789470198502 ""}
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Timing Analyzer" 0 -1 1789470200067 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus Prime " "Running Quartus Prime EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1789470200067 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Sep 15 21:03:19 2026 " "Processing started: Tue Sep 15 21:03:19 2026" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1789470200067 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1789470200067 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off q1 -c seven_seg " "Command: quartus_eda --read_settings_files=off --write_settings_files=off q1 -c seven_seg" {  } {  } 0 0 "Command: %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1789470200068 ""}
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "EDA Netlist Writer" 0 -1 1789470200811 ""}
+{ "Info" "IWSC_DONE_HDL_GENERATION" "seven_seg.svo /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q1/simulation/questa/ simulation " "Generated file seven_seg.svo in folder \"/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q1/simulation/questa/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1789470200874 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 1  Quartus Prime " "Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "670 " "Peak virtual memory: 670 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1789470200924 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Sep 15 21:03:20 2026 " "Processing ended: Tue Sep 15 21:03:20 2026" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1789470200924 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1789470200924 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1789470200924 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "EDA Netlist Writer" 0 -1 1789470200924 ""}
+{ "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 18 s " "Quartus Prime Full Compilation was successful. 0 errors, 18 warnings" {  } {  } 0 293000 "Quartus Prime %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "EDA Netlist Writer" 0 -1 1789470201633 ""}

Quartus/A1_Q1/db/seven_seg.asm.qmsg

@@ -1,6 +1,6 @@
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1788418657395 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1788418657395 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Sep  3 16:57:37 2026 " "Processing started: Thu Sep  3 16:57:37 2026" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1788418657395 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1788418657395 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off q1 -c seven_seg " "Command: quartus_asm --read_settings_files=off --write_settings_files=off q1 -c seven_seg" {  } {  } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1788418657395 ""}
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1788418658046 ""}
-{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" {  } {  } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1788418662314 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1  Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "525 " "Peak virtual memory: 525 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1788418662476 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Sep  3 16:57:42 2026 " "Processing ended: Thu Sep  3 16:57:42 2026" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1788418662476 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Elapsed time: 00:00:05" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1788418662476 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Total CPU time (on all processors): 00:00:05" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1788418662476 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1788418662476 ""}
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1789470425268 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1789470425269 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Sep 15 21:07:05 2026 " "Processing started: Tue Sep 15 21:07:05 2026" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1789470425269 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1789470425269 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off q1 -c seven_seg " "Command: quartus_asm --read_settings_files=off --write_settings_files=off q1 -c seven_seg" {  } {  } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1789470425269 ""}
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1789470425929 ""}
+{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" {  } {  } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1789470430344 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1  Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "514 " "Peak virtual memory: 514 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1789470430525 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Sep 15 21:07:10 2026 " "Processing ended: Tue Sep 15 21:07:10 2026" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1789470430525 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Elapsed time: 00:00:05" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1789470430525 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Total CPU time (on all processors): 00:00:05" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1789470430525 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1789470430525 ""}

Quartus/A1_Q1/db/seven_seg.cmp.logdb

@@ -29,23 +29,34 @@ IO_RULES,LOC_SUPPORT_IO_STD,PASS,IO_000009,I/O Properties Checks for One I/O,The
 IO_RULES,SINGLE_ENDED_OUTPUTS_LAB_ROWS_FROM_DIFF_IO,INAPPLICABLE,IO_000034,SI Related Distance Checks,Single-ended outputs should be 0 LAB row(s) away from a differential I/O.,High,No Differential I/O Standard assignments found.,,I/O,,
 IO_RULES,DEV_IO_RULE_OCT_DISCLAIMER,,,,,,,,,,
 IO_RULES_MATRIX,Pin/Rules,IO_000002;IO_000001;IO_000003;IO_000004;IO_000005;IO_000006;IO_000007;IO_000008;IO_000047;IO_000046;IO_000045;IO_000027;IO_000026;IO_000024;IO_000023;IO_000022;IO_000021;IO_000020;IO_000019;IO_000018;IO_000015;IO_000014;IO_000013;IO_000012;IO_000011;IO_000010;IO_000009;IO_000034,
-IO_RULES_MATRIX,Total Pass,0;13;13;0;0;13;13;0;0;0;0;0;0;8;0;0;0;0;8;0;0;0;0;8;0;13;13;0,
+IO_RULES_MATRIX,Total Pass,0;22;22;0;0;24;22;0;0;0;0;0;0;16;0;0;0;0;16;0;0;0;0;16;0;24;24;0,
 IO_RULES_MATRIX,Total Unchecked,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
-IO_RULES_MATRIX,Total Inapplicable,13;0;0;13;13;0;0;13;13;13;13;13;13;5;13;13;13;13;5;13;13;13;13;5;13;0;0;13,
+IO_RULES_MATRIX,Total Inapplicable,24;2;2;24;24;0;2;24;24;24;24;24;24;8;24;24;24;24;8;24;24;24;24;8;24;0;0;24,
 IO_RULES_MATRIX,Total Fail,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
-IO_RULES_MATRIX,segments[0],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,segments[1],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,segments[2],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,segments[3],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,segments[4],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,segments[5],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,segments[6],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,segments[7],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,num[0],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,rbi_inv[0],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,num[3],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,num[1],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,num[2],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
+IO_RULES_MATRIX,seg_b[0],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable,
+IO_RULES_MATRIX,seg_b[1],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable,
+IO_RULES_MATRIX,seg_b[2],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable,
+IO_RULES_MATRIX,seg_b[3],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable,
+IO_RULES_MATRIX,seg_b[4],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable,
+IO_RULES_MATRIX,seg_b[5],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable,
+IO_RULES_MATRIX,seg_b[6],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable,
+IO_RULES_MATRIX,seg_b[7],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable,
+IO_RULES_MATRIX,seg_a[0],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable,
+IO_RULES_MATRIX,seg_a[1],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable,
+IO_RULES_MATRIX,seg_a[2],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable,
+IO_RULES_MATRIX,seg_a[3],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable,
+IO_RULES_MATRIX,seg_a[4],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable,
+IO_RULES_MATRIX,seg_a[5],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable,
+IO_RULES_MATRIX,seg_a[6],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable,
+IO_RULES_MATRIX,seg_a[7],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable,
+IO_RULES_MATRIX,b[0],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
+IO_RULES_MATRIX,b[1],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
+IO_RULES_MATRIX,b[2],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
+IO_RULES_MATRIX,b[3],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
+IO_RULES_MATRIX,a[0],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
+IO_RULES_MATRIX,a[1],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
+IO_RULES_MATRIX,a[2],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
+IO_RULES_MATRIX,a[3],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
 IO_RULES_SUMMARY,Total I/O Rules,28,
 IO_RULES_SUMMARY,Number of I/O Rules Passed,9,
 IO_RULES_SUMMARY,Number of I/O Rules Failed,0,

Quartus/A1_Q1/db/seven_seg.db_info

@@ -1,3 +1,3 @@
 Quartus_Version = Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
 Version_Index = 604268800
-Creation_Time = Thu Sep  3 19:21:31 2026
+Creation_Time = Wed Sep 16 09:35:09 2026

Quartus/A1_Q1/db/seven_seg.eda.qmsg

@@ -1,6 +1,6 @@
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1788418670701 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus Prime " "Running Quartus Prime EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1788418670701 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Sep  3 16:57:50 2026 " "Processing started: Thu Sep  3 16:57:50 2026" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1788418670701 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1788418670701 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off q1 -c seven_seg " "Command: quartus_eda --read_settings_files=off --write_settings_files=off q1 -c seven_seg" {  } {  } 0 0 "Command: %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1788418670702 ""}
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "EDA Netlist Writer" 0 -1 1788418671436 ""}
-{ "Info" "IWSC_DONE_HDL_GENERATION" "seven_seg.svo /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q1/simulation/questa/ simulation " "Generated file seven_seg.svo in folder \"/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q1/simulation/questa/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1788418671488 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 1  Quartus Prime " "Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "658 " "Peak virtual memory: 658 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1788418671527 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Sep  3 16:57:51 2026 " "Processing ended: Thu Sep  3 16:57:51 2026" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1788418671527 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1788418671527 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1788418671527 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "EDA Netlist Writer" 0 -1 1788418671527 ""}
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1789470439149 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus Prime " "Running Quartus Prime EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1789470439150 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Sep 15 21:07:18 2026 " "Processing started: Tue Sep 15 21:07:18 2026" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1789470439150 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1789470439150 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off q1 -c seven_seg " "Command: quartus_eda --read_settings_files=off --write_settings_files=off q1 -c seven_seg" {  } {  } 0 0 "Command: %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1789470439150 ""}
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "EDA Netlist Writer" 0 -1 1789470439916 ""}
+{ "Info" "IWSC_DONE_HDL_GENERATION" "seven_seg.svo /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q1/simulation/questa/ simulation " "Generated file seven_seg.svo in folder \"/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q1/simulation/questa/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1789470439976 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 1  Quartus Prime " "Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "670 " "Peak virtual memory: 670 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1789470440029 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Sep 15 21:07:20 2026 " "Processing ended: Tue Sep 15 21:07:20 2026" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1789470440029 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1789470440029 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1789470440029 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "EDA Netlist Writer" 0 -1 1789470440029 ""}

Quartus/A1_Q1/db/seven_seg.fit.qmsg

@@ -1,43 +1,46 @@
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1788418628799 ""}
-{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1788418628800 ""}
-{ "Info" "IMPP_MPP_USER_DEVICE" "seven_seg 5CGXFC5C6F27C7 " "Selected device 5CGXFC5C6F27C7 for design \"seven_seg\"" {  } {  } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1788418628804 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1788418628870 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1788418628870 ""}
-{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1788418629270 ""}
-{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." {  } {  } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1788418629302 ""}
-{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" {  } {  } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1788418629350 ""}
-{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_START_INFO" "" "Starting Fitter periphery placement operations" {  } {  } 0 184020 "Starting Fitter periphery placement operations" 0 0 "Fitter" 0 -1 1788418636105 ""}
-{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_END_INFO" "00:00:00 " "Fitter periphery placement operations ending: elapsed time is 00:00:00" {  } {  } 0 184021 "Fitter periphery placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1788418636123 ""}
-{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" {  } {  } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1788418636125 ""}
-{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" {  } {  } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1788418636125 ""}
-{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" {  } {  } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1788418636126 ""}
-{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" {  } {  } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1788418636126 ""}
-{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" {  } {  } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1788418636126 ""}
-{ "Extra Info" "IFSAC_FSAC_START_IO_MAC_RAM_PACKING" "" "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" {  } {  } 1 176246 "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1788418636126 ""}
-{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MAC_RAM_PACKING" "" "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" {  } {  } 1 176247 "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1788418636126 ""}
-{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" {  } {  } 1 176219 "No registers were packed into other blocks" 0 0 "Design Software" 0 -1 1788418636126 ""}  } {  } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1788418636126 ""}
-{ "Info" "IFSV_FITTER_PREPARATION_END" "00:00:07 " "Fitter preparation operations ending: elapsed time is 00:00:07" {  } {  } 0 11798 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1788418636143 ""}
-{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "seven_seg.sdc " "Synopsys Design Constraints File file not found: 'seven_seg.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." {  } {  } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1788418642018 ""}
-{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" {  } {  } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1788418642018 ""}
-{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." {  } {  } 0 332096 "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." 0 0 "Fitter" 0 -1 1788418642019 ""}
-{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." {  } {  } 0 332068 "No clocks defined in design." 0 0 "Fitter" 0 -1 1788418642019 ""}
-{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" {  } {  } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1788418642020 ""}
-{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." {  } {  } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Fitter" 0 -1 1788418642020 ""}
-{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." {  } {  } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1788418642021 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" {  } {  } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1788418642023 ""}
-{ "Info" "IVPR20K_VPR_APL_ENABLED" "" "The Fitter is using Advanced Physical Optimization." {  } {  } 0 14951 "The Fitter is using Advanced Physical Optimization." 0 0 "Fitter" 0 -1 1788418642102 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:01 " "Fitter placement preparation operations ending: elapsed time is 00:00:01" {  } {  } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1788418642704 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" {  } {  } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1788418643216 ""}
-{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" {  } {  } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1788418643462 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1788418643462 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" {  } {  } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1788418644424 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X46_Y0 X56_Y11 " "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X46_Y0 to location X56_Y11" {  } { { "loc" "" { Generic "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q1/" { { 1 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X46_Y0 to location X56_Y11"} { { 12 { 0 ""} 46 0 11 12 }  }  }  }  } }  } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1788418649870 ""}  } {  } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1788418649870 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" {  } {  } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1788418650096 ""} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Optimizations that may affect the design's timing were skipped" {  } {  } 0 170200 "Optimizations that may affect the design's timing were skipped" 0 0 "Design Software" 0 -1 1788418650096 ""}  } {  } 0 170199 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1788418650096 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Fitter routing operations ending: elapsed time is 00:00:01" {  } {  } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1788418650098 ""}
-{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.08 " "Total time spent on timing analysis during the Fitter is 0.08 seconds." {  } {  } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1788418651194 ""}
-{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1788418651229 ""}
-{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1788418651579 ""}
-{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1788418651580 ""}
-{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1788418652299 ""}
-{ "Info" "IFSV_FITTER_POST_OPERATION_END" "00:00:04 " "Fitter post-fit operations ending: elapsed time is 00:00:04" {  } {  } 0 11801 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1788418655001 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 5 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "1384 " "Peak virtual memory: 1384 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1788418655800 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Sep  3 16:57:35 2026 " "Processing ended: Thu Sep  3 16:57:35 2026" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1788418655800 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:27 " "Elapsed time: 00:00:27" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1788418655800 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:39 " "Total CPU time (on all processors): 00:00:39" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1788418655800 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1788418655800 ""}
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1789470394884 ""}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1789470394885 ""}
+{ "Info" "IMPP_MPP_USER_DEVICE" "seven_seg 5CGXFC5C6F27C7 " "Selected device 5CGXFC5C6F27C7 for design \"seven_seg\"" {  } {  } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1789470394891 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1789470394960 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1789470394960 ""}
+{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1789470395386 ""}
+{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." {  } {  } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1789470395414 ""}
+{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" {  } {  } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1789470395463 ""}
+{ "Critical Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "2 24 " "No exact pin location assignment(s) for 2 pins of 24 total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report." {  } {  } 1 169085 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report." 0 0 "Fitter" 0 -1 1789470395729 ""}
+{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_START_INFO" "" "Starting Fitter periphery placement operations" {  } {  } 0 184020 "Starting Fitter periphery placement operations" 0 0 "Fitter" 0 -1 1789470402308 ""}
+{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_END_INFO" "00:00:00 " "Fitter periphery placement operations ending: elapsed time is 00:00:00" {  } {  } 0 184021 "Fitter periphery placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1789470402364 ""}
+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" {  } {  } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1789470402367 ""}
+{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" {  } {  } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1789470402367 ""}
+{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" {  } {  } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1789470402367 ""}
+{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" {  } {  } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1789470402367 ""}
+{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" {  } {  } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1789470402368 ""}
+{ "Extra Info" "IFSAC_FSAC_START_IO_MAC_RAM_PACKING" "" "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" {  } {  } 1 176246 "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1789470402368 ""}
+{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MAC_RAM_PACKING" "" "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" {  } {  } 1 176247 "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1789470402368 ""}
+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" {  } {  } 1 176219 "No registers were packed into other blocks" 0 0 "Design Software" 0 -1 1789470402368 ""}  } {  } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1789470402368 ""}
+{ "Warning" "WCUT_CUT_UNATTACHED_ASGN" "" "Ignored locations or region assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "rbi\[0\] " "Node \"rbi\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/oliver/altera_lite/25.1std/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/oliver/altera_lite/25.1std/quartus/linux64/Assignment Editor.qase" 1 { { 0 "rbi\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1789470402400 ""}  } {  } 0 15705 "Ignored locations or region assignments to the following nodes" 0 0 "Fitter" 0 -1 1789470402400 ""}
+{ "Info" "IFSV_FITTER_PREPARATION_END" "00:00:07 " "Fitter preparation operations ending: elapsed time is 00:00:07" {  } {  } 0 11798 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1789470402401 ""}
+{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "seven_seg.sdc " "Synopsys Design Constraints File file not found: 'seven_seg.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." {  } {  } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1789470408747 ""}
+{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" {  } {  } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1789470408747 ""}
+{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." {  } {  } 0 332096 "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." 0 0 "Fitter" 0 -1 1789470408748 ""}
+{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." {  } {  } 0 332068 "No clocks defined in design." 0 0 "Fitter" 0 -1 1789470408748 ""}
+{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" {  } {  } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1789470408749 ""}
+{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." {  } {  } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Fitter" 0 -1 1789470408749 ""}
+{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." {  } {  } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1789470408750 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" {  } {  } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1789470408753 ""}
+{ "Info" "IVPR20K_VPR_APL_ENABLED" "" "The Fitter is using Advanced Physical Optimization." {  } {  } 0 14951 "The Fitter is using Advanced Physical Optimization." 0 0 "Fitter" 0 -1 1789470408849 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:01 " "Fitter placement preparation operations ending: elapsed time is 00:00:01" {  } {  } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1789470409568 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" {  } {  } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1789470410209 ""}
+{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" {  } {  } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1789470410510 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1789470410511 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" {  } {  } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1789470411531 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X57_Y0 X68_Y11 " "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X57_Y0 to location X68_Y11" {  } { { "loc" "" { Generic "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q1/" { { 1 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X57_Y0 to location X68_Y11"} { { 12 { 0 ""} 57 0 12 12 }  }  }  }  } }  } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1789470417297 ""}  } {  } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1789470417297 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" {  } {  } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1789470417541 ""} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Optimizations that may affect the design's timing were skipped" {  } {  } 0 170200 "Optimizations that may affect the design's timing were skipped" 0 0 "Design Software" 0 -1 1789470417541 ""}  } {  } 0 170199 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1789470417541 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Fitter routing operations ending: elapsed time is 00:00:01" {  } {  } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1789470417543 ""}
+{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.08 " "Total time spent on timing analysis during the Fitter is 0.08 seconds." {  } {  } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1789470418730 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1789470418762 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1789470419148 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1789470419148 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1789470419928 ""}
+{ "Info" "IFSV_FITTER_POST_OPERATION_END" "00:00:04 " "Fitter post-fit operations ending: elapsed time is 00:00:04" {  } {  } 0 11801 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1789470422810 ""}
+{ "Warning" "WFITCC_FITCC_IGNORED_ASSIGNMENT" "" "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." {  } {  } 0 171167 "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." 0 0 "Fitter" 0 -1 1789470423088 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 9 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 9 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "1392 " "Peak virtual memory: 1392 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1789470423652 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Sep 15 21:07:03 2026 " "Processing ended: Tue Sep 15 21:07:03 2026" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1789470423652 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:29 " "Elapsed time: 00:00:29" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1789470423652 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:41 " "Total CPU time (on all processors): 00:00:41" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1789470423652 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1789470423652 ""}

Quartus/A1_Q1/db/seven_seg.hier_info

@@ -1,4 +1,77 @@
-|seven_seg
+|seven_seg_2digit
+b[0] => b[0].IN1
+b[1] => b[1].IN1
+b[2] => b[2].IN1
+b[3] => b[3].IN1
+a[0] => a[0].IN1
+a[1] => a[1].IN1
+a[2] => a[2].IN1
+a[3] => a[3].IN1
+seg_b[0] <= seven_seg:left_digit.segments
+seg_b[1] <= seven_seg:left_digit.segments
+seg_b[2] <= seven_seg:left_digit.segments
+seg_b[3] <= seven_seg:left_digit.segments
+seg_b[4] <= seven_seg:left_digit.segments
+seg_b[5] <= seven_seg:left_digit.segments
+seg_b[6] <= seven_seg:left_digit.segments
+seg_b[7] <= seven_seg:left_digit.segments
+seg_a[0] <= seven_seg:right_digit.segments
+seg_a[1] <= seven_seg:right_digit.segments
+seg_a[2] <= seven_seg:right_digit.segments
+seg_a[3] <= seven_seg:right_digit.segments
+seg_a[4] <= seven_seg:right_digit.segments
+seg_a[5] <= seven_seg:right_digit.segments
+seg_a[6] <= seven_seg:right_digit.segments
+seg_a[7] <= seven_seg:right_digit.segments
+
+
+|seven_seg_2digit|seven_seg:left_digit
+num[0] => Decoder0.IN3
+num[0] => Mux0.IN19
+num[0] => Mux1.IN19
+num[0] => Mux2.IN19
+num[0] => Mux3.IN19
+num[0] => Mux4.IN19
+num[0] => Mux5.IN19
+num[1] => Decoder0.IN2
+num[1] => Mux0.IN18
+num[1] => Mux1.IN18
+num[1] => Mux2.IN18
+num[1] => Mux3.IN18
+num[1] => Mux4.IN18
+num[1] => Mux5.IN18
+num[2] => Decoder0.IN1
+num[2] => Mux0.IN17
+num[2] => Mux1.IN17
+num[2] => Mux2.IN17
+num[2] => Mux3.IN17
+num[2] => Mux4.IN17
+num[2] => Mux5.IN17
+num[3] => Decoder0.IN0
+num[3] => Mux0.IN16
+num[3] => Mux1.IN16
+num[3] => Mux2.IN16
+num[3] => Mux3.IN16
+num[3] => Mux4.IN16
+num[3] => Mux5.IN16
+rbi_inv[0] => Mux0.IN15
+rbi_inv[0] => Mux1.IN15
+rbi_inv[0] => Mux2.IN15
+rbi_inv[0] => Mux3.IN15
+rbi_inv[0] => Mux4.IN15
+rbi_inv[0] => Mux5.IN15
+rbi_inv[0] => segments.DATAB
+segments[0] <= segments.DB_MAX_OUTPUT_PORT_TYPE
+segments[1] <= Mux5.DB_MAX_OUTPUT_PORT_TYPE
+segments[2] <= Mux4.DB_MAX_OUTPUT_PORT_TYPE
+segments[3] <= Mux3.DB_MAX_OUTPUT_PORT_TYPE
+segments[4] <= Mux2.DB_MAX_OUTPUT_PORT_TYPE
+segments[5] <= Mux1.DB_MAX_OUTPUT_PORT_TYPE
+segments[6] <= Mux0.DB_MAX_OUTPUT_PORT_TYPE
+segments[7] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|seven_seg_2digit|seven_seg:right_digit
 num[0] => Decoder0.IN3
 num[0] => Mux0.IN19
 num[0] => Mux1.IN19

Quartus/A1_Q1/db/seven_seg.lpc.html

@@ -15,4 +15,36 @@
 <TH>Input only Bidir</TH>
 <TH>Output only Bidir</TH>
 </TR>
+<TR >
+<TD >right_digit</TD>
+<TD >5</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >1</TD>
+<TD >8</TD>
+<TD >1</TD>
+<TD >1</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >left_digit</TD>
+<TD >5</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >1</TD>
+<TD >8</TD>
+<TD >1</TD>
+<TD >1</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
 </TABLE>

Quartus/A1_Q1/db/seven_seg.lpc.txt

@@ -1,5 +1,8 @@
-+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
 ; Legal Partition Candidates                                                                                                                                                                                       ;
-+-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
++-------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
 ; Hierarchy   ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ;
-+-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
++-------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
+; right_digit ; 5     ; 1              ; 0            ; 1              ; 8      ; 1               ; 1             ; 1               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; left_digit  ; 5     ; 1              ; 0            ; 1              ; 8      ; 1               ; 1             ; 1               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
++-------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+

Quartus/A1_Q1/db/seven_seg.map.qmsg

@@ -1,11 +1,13 @@
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1788418615772 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1788418615772 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Sep  3 16:56:55 2026 " "Processing started: Thu Sep  3 16:56:55 2026" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1788418615772 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1788418615772 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off q1 -c seven_seg " "Command: quartus_map --read_settings_files=on --write_settings_files=off q1 -c seven_seg" {  } {  } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1788418615773 ""}
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1788418616096 ""}
-{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1788418616097 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "seven_seg.sv 1 1 " "Found 1 design units, including 1 entities, in source file seven_seg.sv" { { "Info" "ISGN_ENTITY_NAME" "1 seven_seg " "Found entity 1: seven_seg" {  } { { "seven_seg.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q1/seven_seg.sv" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1788418625920 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1788418625920 ""}
-{ "Info" "ISGN_START_ELABORATION_TOP" "seven_seg " "Elaborating entity \"seven_seg\" for the top level hierarchy" {  } {  } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1788418626051 ""}
-{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" {  } {  } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1788418626737 ""}
-{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" {  } {  } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1788418627068 ""}  } {  } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1788418627068 ""}
-{ "Info" "ICUT_CUT_TM_SUMMARY" "21 " "Implemented 21 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "5 " "Implemented 5 input pins" {  } {  } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1788418627106 ""} { "Info" "ICUT_CUT_TM_OPINS" "8 " "Implemented 8 output pins" {  } {  } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1788418627106 ""} { "Info" "ICUT_CUT_TM_LCELLS" "8 " "Implemented 8 logic cells" {  } {  } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1788418627106 ""}  } {  } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1788418627106 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1  Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "436 " "Peak virtual memory: 436 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1788418627114 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Sep  3 16:57:07 2026 " "Processing ended: Thu Sep  3 16:57:07 2026" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1788418627114 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:12 " "Elapsed time: 00:00:12" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1788418627114 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:27 " "Total CPU time (on all processors): 00:00:27" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1788418627114 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1788418627114 ""}
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1789470382407 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1789470382407 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Sep 15 21:06:22 2026 " "Processing started: Tue Sep 15 21:06:22 2026" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1789470382407 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1789470382407 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off q1 -c seven_seg " "Command: quartus_map --read_settings_files=on --write_settings_files=off q1 -c seven_seg" {  } {  } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1789470382408 ""}
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1789470382748 ""}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1789470382748 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "seven_seg.sv 2 2 " "Found 2 design units, including 2 entities, in source file seven_seg.sv" { { "Info" "ISGN_ENTITY_NAME" "1 seven_seg " "Found entity 1: seven_seg" {  } { { "seven_seg.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q1/seven_seg.sv" 4 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1789470391822 ""} { "Info" "ISGN_ENTITY_NAME" "2 seven_seg_2digit " "Found entity 2: seven_seg_2digit" {  } { { "seven_seg.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q1/seven_seg.sv" 32 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1789470391822 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1789470391822 ""}
+{ "Info" "ISGN_START_ELABORATION_TOP" "seven_seg_2digit " "Elaborating entity \"seven_seg_2digit\" for the top level hierarchy" {  } {  } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1789470391962 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "seven_seg seven_seg:left_digit " "Elaborating entity \"seven_seg\" for hierarchy \"seven_seg:left_digit\"" {  } { { "seven_seg.sv" "left_digit" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q1/seven_seg.sv" 45 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1789470391968 ""}
+{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "seg_a\[0\] GND " "Pin \"seg_a\[0\]\" is stuck at GND" {  } { { "seven_seg.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q1/seven_seg.sv" 36 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1789470392591 "|seven_seg_2digit|seg_a[0]"}  } {  } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Analysis & Synthesis" 0 -1 1789470392591 ""}
+{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" {  } {  } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1789470392705 ""}
+{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" {  } {  } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1789470393089 ""}  } {  } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1789470393089 ""}
+{ "Info" "ICUT_CUT_TM_SUMMARY" "39 " "Implemented 39 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "8 " "Implemented 8 input pins" {  } {  } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1789470393122 ""} { "Info" "ICUT_CUT_TM_OPINS" "16 " "Implemented 16 output pins" {  } {  } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1789470393122 ""} { "Info" "ICUT_CUT_TM_LCELLS" "15 " "Implemented 15 logic cells" {  } {  } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1789470393122 ""}  } {  } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1789470393122 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 3 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "439 " "Peak virtual memory: 439 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1789470393128 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Sep 15 21:06:33 2026 " "Processing ended: Tue Sep 15 21:06:33 2026" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1789470393128 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:11 " "Elapsed time: 00:00:11" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1789470393128 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:25 " "Total CPU time (on all processors): 00:00:25" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1789470393128 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1789470393128 ""}

Quartus/A1_Q1/db/seven_seg.sta.qmsg

@@ -1,61 +1,61 @@
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1788418663922 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus Prime " "Running Quartus Prime Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1788418663923 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Sep  3 16:57:43 2026 " "Processing started: Thu Sep  3 16:57:43 2026" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1788418663923 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Timing Analyzer" 0 -1 1788418663923 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta q1 -c seven_seg " "Command: quartus_sta q1 -c seven_seg" {  } {  } 0 0 "Command: %1!s!" 0 0 "Timing Analyzer" 0 -1 1788418663923 ""}
-{ "Info" "0" "" "qsta_default_script.tcl version: #1" {  } {  } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Timing Analyzer" 0 0 1788418663978 ""}
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Timing Analyzer" 0 -1 1788418664459 ""}
-{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Timing Analyzer" 0 -1 1788418664459 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1788418664532 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1788418664532 ""}
-{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "seven_seg.sdc " "Synopsys Design Constraints File file not found: 'seven_seg.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." {  } {  } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Timing Analyzer" 0 -1 1788418665100 ""}
-{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" {  } {  } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1788418665100 ""}
-{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." {  } {  } 0 332096 "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1788418665101 ""}
-{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." {  } {  } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1788418665101 ""}
-{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" {  } {  } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Timing Analyzer" 0 -1 1788418665101 ""}
-{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." {  } {  } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1788418665101 ""}
-{ "Info" "0" "" "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" {  } {  } 0 0 "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Timing Analyzer" 0 0 1788418665102 ""}
-{ "Info" "ISTA_NO_CLOCKS_TO_REPORT" "" "No clocks to report" {  } {  } 0 332159 "No clocks to report" 0 0 "Timing Analyzer" 0 -1 1788418665106 ""}
-{ "Info" "0" "" "Analyzing Slow 1100mV 85C Model" {  } {  } 0 0 "Analyzing Slow 1100mV 85C Model" 0 0 "Timing Analyzer" 0 0 1788418665107 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788418665108 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788418665111 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788418665112 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788418665113 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788418665114 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788418665114 ""}
-{ "Info" "0" "" "Analyzing Slow 1100mV 0C Model" {  } {  } 0 0 "Analyzing Slow 1100mV 0C Model" 0 0 "Timing Analyzer" 0 0 1788418665117 ""}
-{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1788418665154 ""}
-{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1788418666438 ""}
-{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" {  } {  } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1788418666534 ""}
-{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." {  } {  } 0 332096 "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1788418666534 ""}
-{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." {  } {  } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1788418666534 ""}
-{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." {  } {  } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1788418666535 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788418666535 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788418666537 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788418666538 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788418666539 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788418666539 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788418666540 ""}
-{ "Info" "0" "" "Analyzing Fast 1100mV 85C Model" {  } {  } 0 0 "Analyzing Fast 1100mV 85C Model" 0 0 "Timing Analyzer" 0 0 1788418666542 ""}
-{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1788418666803 ""}
-{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1788418667501 ""}
-{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" {  } {  } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1788418667545 ""}
-{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." {  } {  } 0 332096 "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1788418667546 ""}
-{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." {  } {  } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1788418667546 ""}
-{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." {  } {  } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1788418667546 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788418667547 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788418667548 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788418667549 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788418667550 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788418667550 ""}
-{ "Info" "0" "" "Analyzing Fast 1100mV 0C Model" {  } {  } 0 0 "Analyzing Fast 1100mV 0C Model" 0 0 "Timing Analyzer" 0 0 1788418667552 ""}
-{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" {  } {  } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1788418667701 ""}
-{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." {  } {  } 0 332096 "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1788418667702 ""}
-{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." {  } {  } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1788418667702 ""}
-{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." {  } {  } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1788418667702 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788418667703 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788418667704 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788418667705 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788418667705 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788418667706 ""}
-{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1788418669108 ""}
-{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1788418669108 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 6 s Quartus Prime " "Quartus Prime Timing Analyzer was successful. 0 errors, 6 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "780 " "Peak virtual memory: 780 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1788418669130 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Sep  3 16:57:49 2026 " "Processing ended: Thu Sep  3 16:57:49 2026" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1788418669130 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Elapsed time: 00:00:06" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1788418669130 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Total CPU time (on all processors): 00:00:05" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1788418669130 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Timing Analyzer" 0 -1 1788418669130 ""}
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1789470432010 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus Prime " "Running Quartus Prime Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1789470432010 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Sep 15 21:07:11 2026 " "Processing started: Tue Sep 15 21:07:11 2026" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1789470432010 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Timing Analyzer" 0 -1 1789470432010 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta q1 -c seven_seg " "Command: quartus_sta q1 -c seven_seg" {  } {  } 0 0 "Command: %1!s!" 0 0 "Timing Analyzer" 0 -1 1789470432011 ""}
+{ "Info" "0" "" "qsta_default_script.tcl version: #1" {  } {  } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Timing Analyzer" 0 0 1789470432068 ""}
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Timing Analyzer" 0 -1 1789470432597 ""}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Timing Analyzer" 0 -1 1789470432598 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1789470432666 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1789470432666 ""}
+{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "seven_seg.sdc " "Synopsys Design Constraints File file not found: 'seven_seg.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." {  } {  } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Timing Analyzer" 0 -1 1789470433270 ""}
+{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" {  } {  } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1789470433271 ""}
+{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." {  } {  } 0 332096 "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1789470433271 ""}
+{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." {  } {  } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1789470433271 ""}
+{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" {  } {  } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Timing Analyzer" 0 -1 1789470433272 ""}
+{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." {  } {  } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1789470433272 ""}
+{ "Info" "0" "" "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" {  } {  } 0 0 "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Timing Analyzer" 0 0 1789470433273 ""}
+{ "Info" "ISTA_NO_CLOCKS_TO_REPORT" "" "No clocks to report" {  } {  } 0 332159 "No clocks to report" 0 0 "Timing Analyzer" 0 -1 1789470433277 ""}
+{ "Info" "0" "" "Analyzing Slow 1100mV 85C Model" {  } {  } 0 0 "Analyzing Slow 1100mV 85C Model" 0 0 "Timing Analyzer" 0 0 1789470433278 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789470433279 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789470433283 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789470433284 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789470433287 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789470433288 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789470433289 ""}
+{ "Info" "0" "" "Analyzing Slow 1100mV 0C Model" {  } {  } 0 0 "Analyzing Slow 1100mV 0C Model" 0 0 "Timing Analyzer" 0 0 1789470433293 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1789470433344 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1789470434738 ""}
+{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" {  } {  } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1789470434835 ""}
+{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." {  } {  } 0 332096 "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1789470434835 ""}
+{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." {  } {  } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1789470434835 ""}
+{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." {  } {  } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1789470434835 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789470434836 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789470434837 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789470434838 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789470434839 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789470434840 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789470434840 ""}
+{ "Info" "0" "" "Analyzing Fast 1100mV 85C Model" {  } {  } 0 0 "Analyzing Fast 1100mV 85C Model" 0 0 "Timing Analyzer" 0 0 1789470434842 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1789470435111 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1789470435850 ""}
+{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" {  } {  } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1789470435895 ""}
+{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." {  } {  } 0 332096 "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1789470435895 ""}
+{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." {  } {  } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1789470435895 ""}
+{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." {  } {  } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1789470435895 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789470435897 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789470435898 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789470435899 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789470435899 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789470435900 ""}
+{ "Info" "0" "" "Analyzing Fast 1100mV 0C Model" {  } {  } 0 0 "Analyzing Fast 1100mV 0C Model" 0 0 "Timing Analyzer" 0 0 1789470435903 ""}
+{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" {  } {  } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1789470436058 ""}
+{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." {  } {  } 0 332096 "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1789470436058 ""}
+{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." {  } {  } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1789470436058 ""}
+{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." {  } {  } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1789470436058 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789470436059 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789470436060 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789470436061 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789470436062 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789470436062 ""}
+{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1789470437535 ""}
+{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1789470437536 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 6 s Quartus Prime " "Quartus Prime Timing Analyzer was successful. 0 errors, 6 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "769 " "Peak virtual memory: 769 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1789470437560 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Sep 15 21:07:17 2026 " "Processing ended: Tue Sep 15 21:07:17 2026" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1789470437560 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Elapsed time: 00:00:06" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1789470437560 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:06 " "Total CPU time (on all processors): 00:00:06" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1789470437560 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Timing Analyzer" 0 -1 1789470437560 ""}

Quartus/A1_Q1/db/seven_seg.tmw_info

@@ -1,4 +0,0 @@
-start_full_compilation:s
-start_assembler:s-start_full_compilation
-start_timing_analyzer:s-start_full_compilation
-start_eda_netlist_writer:s-start_full_compilation

Quartus/A1_Q1/db/seven_seg_partition_pins.json

@@ -4,55 +4,95 @@
 			"name" : "Top",
 			"pins" : [
 				{
-					"name" : "segments[0]",
+					"name" : "seg_b[0]",
 					"strict" : false
 				},
 				{
-					"name" : "segments[1]",
+					"name" : "seg_b[1]",
 					"strict" : false
 				},
 				{
-					"name" : "segments[2]",
+					"name" : "seg_b[2]",
 					"strict" : false
 				},
 				{
-					"name" : "segments[3]",
+					"name" : "seg_b[3]",
 					"strict" : false
 				},
 				{
-					"name" : "segments[4]",
+					"name" : "seg_b[4]",
 					"strict" : false
 				},
 				{
-					"name" : "segments[5]",
+					"name" : "seg_b[5]",
 					"strict" : false
 				},
 				{
-					"name" : "segments[6]",
+					"name" : "seg_b[6]",
 					"strict" : false
 				},
 				{
-					"name" : "segments[7]",
+					"name" : "seg_b[7]",
 					"strict" : false
 				},
 				{
-					"name" : "num[0]",
+					"name" : "seg_a[1]",
 					"strict" : false
 				},
 				{
-					"name" : "rbi_inv[0]",
+					"name" : "seg_a[2]",
 					"strict" : false
 				},
 				{
-					"name" : "num[3]",
+					"name" : "seg_a[3]",
 					"strict" : false
 				},
 				{
-					"name" : "num[1]",
+					"name" : "seg_a[4]",
 					"strict" : false
 				},
 				{
-					"name" : "num[2]",
+					"name" : "seg_a[5]",
+					"strict" : false
+				},
+				{
+					"name" : "seg_a[6]",
+					"strict" : false
+				},
+				{
+					"name" : "seg_a[7]",
+					"strict" : false
+				},
+				{
+					"name" : "b[0]",
+					"strict" : false
+				},
+				{
+					"name" : "b[1]",
+					"strict" : false
+				},
+				{
+					"name" : "b[2]",
+					"strict" : false
+				},
+				{
+					"name" : "b[3]",
+					"strict" : false
+				},
+				{
+					"name" : "a[0]",
+					"strict" : false
+				},
+				{
+					"name" : "a[1]",
+					"strict" : false
+				},
+				{
+					"name" : "a[2]",
+					"strict" : false
+				},
+				{
+					"name" : "a[3]",
 					"strict" : false
 				}
 			]

Quartus/A1_Q1/output_files/seven_seg.asm.rpt

@@ -1,5 +1,5 @@
 Assembler report for seven_seg
-Thu Sep  3 16:57:42 2026
+Tue Sep 15 21:07:10 2026
 Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
 
 
@@ -38,9 +38,9 @@ on the Quartus Prime software download page.
 +---------------------------------------------------------------+
 ; Assembler Summary                                             ;
 +-----------------------+---------------------------------------+
-; Assembler Status      ; Successful - Thu Sep  3 16:57:42 2026 ;
+; Assembler Status      ; Successful - Tue Sep 15 21:07:10 2026 ;
 ; Revision Name         ; seven_seg                             ;
-; Top-level Entity Name ; seven_seg                             ;
+; Top-level Entity Name ; seven_seg_2digit                      ;
 ; Family                ; Cyclone V                             ;
 ; Device                ; 5CGXFC5C6F27C7                        ;
 +-----------------------+---------------------------------------+
@@ -67,8 +67,8 @@ on the Quartus Prime software download page.
 +----------------+------------------------+
 ; Option         ; Setting                ;
 +----------------+------------------------+
-; JTAG usercode  ; 0x00781CB4             ;
-; Checksum       ; 0x00781CB4             ;
+; JTAG usercode  ; 0x007840FC             ;
+; Checksum       ; 0x007840FC             ;
 +----------------+------------------------+
 
 
@@ -78,13 +78,13 @@ on the Quartus Prime software download page.
 Info: *******************************************************************
 Info: Running Quartus Prime Assembler
     Info: Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
-    Info: Processing started: Thu Sep  3 16:57:37 2026
+    Info: Processing started: Tue Sep 15 21:07:05 2026
 Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off q1 -c seven_seg
 Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
 Info (115030): Assembler is generating device programming files
 Info: Quartus Prime Assembler was successful. 0 errors, 1 warning
-    Info: Peak virtual memory: 525 megabytes
-    Info: Processing ended: Thu Sep  3 16:57:42 2026
+    Info: Peak virtual memory: 514 megabytes
+    Info: Processing ended: Tue Sep 15 21:07:10 2026
     Info: Elapsed time: 00:00:05
     Info: Total CPU time (on all processors): 00:00:05
 

Quartus/A1_Q1/output_files/seven_seg.done

@@ -1 +1 @@
-Thu Sep  3 16:57:52 2026
+Tue Sep 15 21:07:20 2026

Quartus/A1_Q1/output_files/seven_seg.eda.rpt

@@ -1,5 +1,5 @@
 EDA Netlist Writer report for seven_seg
-Thu Sep  3 16:57:51 2026
+Tue Sep 15 21:07:19 2026
 Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
 
 
@@ -37,9 +37,9 @@ on the Quartus Prime software download page.
 +-------------------------------------------------------------------+
 ; EDA Netlist Writer Summary                                        ;
 +---------------------------+---------------------------------------+
-; EDA Netlist Writer Status ; Successful - Thu Sep  3 16:57:51 2026 ;
+; EDA Netlist Writer Status ; Successful - Tue Sep 15 21:07:19 2026 ;
 ; Revision Name             ; seven_seg                             ;
-; Top-level Entity Name     ; seven_seg                             ;
+; Top-level Entity Name     ; seven_seg_2digit                      ;
 ; Family                    ; Cyclone V                             ;
 ; Simulation Files Creation ; Successful                            ;
 +---------------------------+---------------------------------------+
@@ -81,14 +81,14 @@ on the Quartus Prime software download page.
 Info: *******************************************************************
 Info: Running Quartus Prime EDA Netlist Writer
     Info: Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
-    Info: Processing started: Thu Sep  3 16:57:50 2026
+    Info: Processing started: Tue Sep 15 21:07:18 2026
 Info: Command: quartus_eda --read_settings_files=off --write_settings_files=off q1 -c seven_seg
 Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
 Info (204019): Generated file seven_seg.svo in folder "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q1/simulation/questa/" for EDA simulation tool
 Info: Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning
-    Info: Peak virtual memory: 658 megabytes
-    Info: Processing ended: Thu Sep  3 16:57:51 2026
-    Info: Elapsed time: 00:00:01
+    Info: Peak virtual memory: 670 megabytes
+    Info: Processing ended: Tue Sep 15 21:07:20 2026
+    Info: Elapsed time: 00:00:02
     Info: Total CPU time (on all processors): 00:00:01
 
 

Quartus/A1_Q1/output_files/seven_seg.fit.rpt

@@ -1,5 +1,5 @@
 Fitter report for seven_seg
-Thu Sep  3 16:57:35 2026
+Tue Sep 15 21:07:03 2026
 Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
 
 
@@ -10,27 +10,28 @@ Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
   2. Fitter Summary
   3. Fitter Settings
   4. Parallel Compilation
-  5. Incremental Compilation Preservation Summary
-  6. Incremental Compilation Partition Settings
-  7. Incremental Compilation Placement Preservation
-  8. Pin-Out File
-  9. Fitter Resource Usage Summary
- 10. Fitter Partition Statistics
- 11. Input Pins
- 12. Output Pins
- 13. I/O Bank Usage
- 14. All Package Pins
- 15. I/O Assignment Warnings
- 16. Fitter Resource Utilization by Entity
- 17. Delay Chain Summary
- 18. Pad To Core Delay Chain Fanout
- 19. Routing Usage Summary
- 20. I/O Rules Summary
- 21. I/O Rules Details
- 22. I/O Rules Matrix
- 23. Fitter Device Options
- 24. Operating Settings and Conditions
- 25. Fitter Messages
+  5. Ignored Assignments
+  6. Incremental Compilation Preservation Summary
+  7. Incremental Compilation Partition Settings
+  8. Incremental Compilation Placement Preservation
+  9. Pin-Out File
+ 10. Fitter Resource Usage Summary
+ 11. Fitter Partition Statistics
+ 12. Input Pins
+ 13. Output Pins
+ 14. I/O Bank Usage
+ 15. All Package Pins
+ 16. I/O Assignment Warnings
+ 17. Fitter Resource Utilization by Entity
+ 18. Delay Chain Summary
+ 19. Pad To Core Delay Chain Fanout
+ 20. Routing Usage Summary
+ 21. I/O Rules Summary
+ 22. I/O Rules Details
+ 23. I/O Rules Matrix
+ 24. Fitter Device Options
+ 25. Operating Settings and Conditions
+ 26. Fitter Messages
 
 
 
@@ -57,16 +58,16 @@ on the Quartus Prime software download page.
 +-----------------------------------------------------------------------------------+
 ; Fitter Summary                                                                    ;
 +---------------------------------+-------------------------------------------------+
-; Fitter Status                   ; Successful - Thu Sep  3 16:57:35 2026           ;
+; Fitter Status                   ; Successful - Tue Sep 15 21:07:03 2026           ;
 ; Quartus Prime Version           ; 25.1std.0 Build 1129 10/21/2025 SC Lite Edition ;
 ; Revision Name                   ; seven_seg                                       ;
-; Top-level Entity Name           ; seven_seg                                       ;
+; Top-level Entity Name           ; seven_seg_2digit                                ;
 ; Family                          ; Cyclone V                                       ;
 ; Device                          ; 5CGXFC5C6F27C7                                  ;
 ; Timing Models                   ; Final                                           ;
-; Logic utilization (in ALMs)     ; 5 / 29,080 ( < 1 % )                            ;
+; Logic utilization (in ALMs)     ; 8 / 29,080 ( < 1 % )                            ;
 ; Total registers                 ; 0                                               ;
-; Total pins                      ; 13 / 364 ( 4 % )                                ;
+; Total pins                      ; 24 / 364 ( 7 % )                                ;
 ; Total virtual pins              ; 0                                               ;
 ; Total block memory bits         ; 0 / 4,567,040 ( 0 % )                           ;
 ; Total RAM Blocks                ; 0 / 446 ( 0 % )                                 ;
@@ -156,14 +157,27 @@ on the Quartus Prime software download page.
 +----------------------------+-------------+
 
 
++----------------------------------------------------------------------------------------------+
+; Ignored Assignments                                                                          ;
++--------------+------------------+--------------+------------+---------------+----------------+
+; Name         ; Ignored Entity   ; Ignored From ; Ignored To ; Ignored Value ; Ignored Source ;
++--------------+------------------+--------------+------------+---------------+----------------+
+; Location     ;                  ;              ; rbi[0]     ; PIN_AE19      ; QSF Assignment ;
+; I/O Standard ; seven_seg_2digit ;              ; b          ; 1.2 V         ; QSF Assignment ;
+; I/O Standard ; seven_seg_2digit ;              ; rbi[0]     ; 1.2 V         ; QSF Assignment ;
+; I/O Standard ; seven_seg_2digit ;              ; seg_a      ; 1.2 V         ; QSF Assignment ;
+; I/O Standard ; seven_seg_2digit ;              ; seg_b      ; 1.2 V         ; QSF Assignment ;
++--------------+------------------+--------------+------------+---------------+----------------+
+
+
 +-------------------------------------------------------------------------------------------------+
 ; Incremental Compilation Preservation Summary                                                    ;
 +---------------------+-------------------+----------------------------+--------------------------+
 ; Type                ; Total [A + B]     ; From Design Partitions [A] ; From Rapid Recompile [B] ;
 +---------------------+-------------------+----------------------------+--------------------------+
 ; Placement (by node) ;                   ;                            ;                          ;
-;     -- Requested    ; 0.00 % ( 0 / 35 ) ; 0.00 % ( 0 / 35 )          ; 0.00 % ( 0 / 35 )        ;
-;     -- Achieved     ; 0.00 % ( 0 / 35 ) ; 0.00 % ( 0 / 35 )          ; 0.00 % ( 0 / 35 )        ;
+;     -- Requested    ; 0.00 % ( 0 / 64 ) ; 0.00 % ( 0 / 64 )          ; 0.00 % ( 0 / 64 )        ;
+;     -- Achieved     ; 0.00 % ( 0 / 64 ) ; 0.00 % ( 0 / 64 )          ; 0.00 % ( 0 / 64 )        ;
 ;                     ;                   ;                            ;                          ;
 ; Routing (by net)    ;                   ;                            ;                          ;
 ;     -- Requested    ; 0.00 % ( 0 / 0 )  ; 0.00 % ( 0 / 0 )           ; 0.00 % ( 0 / 0 )         ;
@@ -186,7 +200,7 @@ on the Quartus Prime software download page.
 +--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
 ; Partition Name                 ; Preservation Achieved ; Preservation Level Used ; Netlist Type Used ; Preservation Method ; Notes ;
 +--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
-; Top                            ; 0.00 % ( 0 / 35 )     ; N/A                     ; Source File       ; N/A                 ;       ;
+; Top                            ; 0.00 % ( 0 / 64 )     ; N/A                     ; Source File       ; N/A                 ;       ;
 ; hard_block:auto_generated_inst ; 0.00 % ( 0 / 0 )      ; N/A                     ; Source File       ; N/A                 ;       ;
 +--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
 
@@ -202,14 +216,14 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu
 +-------------------------------------------------------------+--------------------+-------+
 ; Resource                                                    ; Usage              ; %     ;
 +-------------------------------------------------------------+--------------------+-------+
-; Logic utilization (ALMs needed / total ALMs on device)      ; 5 / 29,080         ; < 1 % ;
-; ALMs needed [=A-B+C]                                        ; 5                  ;       ;
+; Logic utilization (ALMs needed / total ALMs on device)      ; 8 / 29,080         ; < 1 % ;
+; ALMs needed [=A-B+C]                                        ; 8                  ;       ;
 ;     [A] ALMs used in final placement [=a+b+c+d]             ; 8 / 29,080         ; < 1 % ;
 ;         [a] ALMs used for LUT logic and registers           ; 0                  ;       ;
 ;         [b] ALMs used for LUT logic                         ; 8                  ;       ;
 ;         [c] ALMs used for registers                         ; 0                  ;       ;
 ;         [d] ALMs used for memory (up to half of total ALMs) ; 0                  ;       ;
-;     [B] Estimate of ALMs recoverable by dense packing       ; 3 / 29,080         ; < 1 % ;
+;     [B] Estimate of ALMs recoverable by dense packing       ; 0 / 29,080         ; 0 %   ;
 ;     [C] Estimate of ALMs unavailable [=a+b+c+d]             ; 0 / 29,080         ; 0 %   ;
 ;         [a] Due to location constrained logic               ; 0                  ;       ;
 ;         [b] Due to LAB-wide signal conflicts                ; 0                  ;       ;
@@ -218,15 +232,15 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu
 ;                                                             ;                    ;       ;
 ; Difficulty packing design                                   ; Low                ;       ;
 ;                                                             ;                    ;       ;
-; Total LABs:  partially or completely used                   ; 2 / 2,908          ; < 1 % ;
-;     -- Logic LABs                                           ; 2                  ;       ;
+; Total LABs:  partially or completely used                   ; 3 / 2,908          ; < 1 % ;
+;     -- Logic LABs                                           ; 3                  ;       ;
 ;     -- Memory LABs (up to half of total LABs)               ; 0                  ;       ;
 ;                                                             ;                    ;       ;
-; Combinational ALUT usage for logic                          ; 9                  ;       ;
+; Combinational ALUT usage for logic                          ; 16                 ;       ;
 ;     -- 7 input functions                                    ; 0                  ;       ;
 ;     -- 6 input functions                                    ; 0                  ;       ;
-;     -- 5 input functions                                    ; 7                  ;       ;
-;     -- 4 input functions                                    ; 1                  ;       ;
+;     -- 5 input functions                                    ; 0                  ;       ;
+;     -- 4 input functions                                    ; 15                 ;       ;
 ;     -- <=3 input functions                                  ; 1                  ;       ;
 ; Combinational ALUT usage for route-throughs                 ; 0                  ;       ;
 ;                                                             ;                    ;       ;
@@ -239,7 +253,7 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu
 ;         -- Routing optimization registers                   ; 0                  ;       ;
 ;                                                             ;                    ;       ;
 ; Virtual pins                                                ; 0                  ;       ;
-; I/O pins                                                    ; 13 / 364           ; 4 %   ;
+; I/O pins                                                    ; 24 / 364           ; 7 %   ;
 ;     -- Clock pins                                           ; 0 / 14             ; 0 %   ;
 ;     -- Dedicated input pins                                 ; 0 / 23             ; 0 %   ;
 ;                                                             ;                    ;       ;
@@ -271,11 +285,11 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu
 ; Impedance control blocks                                    ; 0 / 3              ; 0 %   ;
 ; Hard Memory Controllers                                     ; 0 / 2              ; 0 %   ;
 ; Average interconnect usage (total/H/V)                      ; 0.0% / 0.0% / 0.0% ;       ;
-; Peak interconnect usage (total/H/V)                         ; 0.1% / 0.2% / 0.1% ;       ;
+; Peak interconnect usage (total/H/V)                         ; 0.2% / 0.2% / 0.2% ;       ;
 ; Maximum fan-out                                             ; 8                  ;       ;
 ; Highest non-global fan-out                                  ; 8                  ;       ;
-; Total fan-out                                               ; 60                 ;       ;
-; Average fan-out                                             ; 1.71               ;       ;
+; Total fan-out                                               ; 99                 ;       ;
+; Average fan-out                                             ; 1.55               ;       ;
 +-------------------------------------------------------------+--------------------+-------+
 
 
@@ -284,14 +298,14 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu
 +-------------------------------------------------------------+---------------------+--------------------------------+
 ; Statistic                                                   ; Top                 ; hard_block:auto_generated_inst ;
 +-------------------------------------------------------------+---------------------+--------------------------------+
-; Logic utilization (ALMs needed / total ALMs on device)      ; 5 / 29080 ( < 1 % ) ; 0 / 29080 ( 0 % )              ;
-; ALMs needed [=A-B+C]                                        ; 5                   ; 0                              ;
+; Logic utilization (ALMs needed / total ALMs on device)      ; 8 / 29080 ( < 1 % ) ; 0 / 29080 ( 0 % )              ;
+; ALMs needed [=A-B+C]                                        ; 8                   ; 0                              ;
 ;     [A] ALMs used in final placement [=a+b+c+d]             ; 8 / 29080 ( < 1 % ) ; 0 / 29080 ( 0 % )              ;
 ;         [a] ALMs used for LUT logic and registers           ; 0                   ; 0                              ;
 ;         [b] ALMs used for LUT logic                         ; 8                   ; 0                              ;
 ;         [c] ALMs used for registers                         ; 0                   ; 0                              ;
 ;         [d] ALMs used for memory (up to half of total ALMs) ; 0                   ; 0                              ;
-;     [B] Estimate of ALMs recoverable by dense packing       ; 3 / 29080 ( < 1 % ) ; 0 / 29080 ( 0 % )              ;
+;     [B] Estimate of ALMs recoverable by dense packing       ; 0 / 29080 ( 0 % )   ; 0 / 29080 ( 0 % )              ;
 ;     [C] Estimate of ALMs unavailable [=a+b+c+d]             ; 0 / 29080 ( 0 % )   ; 0 / 29080 ( 0 % )              ;
 ;         [a] Due to location constrained logic               ; 0                   ; 0                              ;
 ;         [b] Due to LAB-wide signal conflicts                ; 0                   ; 0                              ;
@@ -300,15 +314,15 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu
 ;                                                             ;                     ;                                ;
 ; Difficulty packing design                                   ; Low                 ; Low                            ;
 ;                                                             ;                     ;                                ;
-; Total LABs:  partially or completely used                   ; 2 / 2908 ( < 1 % )  ; 0 / 2908 ( 0 % )               ;
-;     -- Logic LABs                                           ; 2                   ; 0                              ;
+; Total LABs:  partially or completely used                   ; 3 / 2908 ( < 1 % )  ; 0 / 2908 ( 0 % )               ;
+;     -- Logic LABs                                           ; 3                   ; 0                              ;
 ;     -- Memory LABs (up to half of total LABs)               ; 0                   ; 0                              ;
 ;                                                             ;                     ;                                ;
-; Combinational ALUT usage for logic                          ; 9                   ; 0                              ;
+; Combinational ALUT usage for logic                          ; 16                  ; 0                              ;
 ;     -- 7 input functions                                    ; 0                   ; 0                              ;
 ;     -- 6 input functions                                    ; 0                   ; 0                              ;
-;     -- 5 input functions                                    ; 7                   ; 0                              ;
-;     -- 4 input functions                                    ; 1                   ; 0                              ;
+;     -- 5 input functions                                    ; 0                   ; 0                              ;
+;     -- 4 input functions                                    ; 15                  ; 0                              ;
 ;     -- <=3 input functions                                  ; 1                   ; 0                              ;
 ; Combinational ALUT usage for route-throughs                 ; 0                   ; 0                              ;
 ; Memory ALUT usage                                           ; 0                   ; 0                              ;
@@ -325,7 +339,7 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu
 ;                                                             ;                     ;                                ;
 ;                                                             ;                     ;                                ;
 ; Virtual pins                                                ; 0                   ; 0                              ;
-; I/O pins                                                    ; 13                  ; 0                              ;
+; I/O pins                                                    ; 24                  ; 0                              ;
 ; I/O registers                                               ; 0                   ; 0                              ;
 ; Total block memory bits                                     ; 0                   ; 0                              ;
 ; Total block memory implementation bits                      ; 0                   ; 0                              ;
@@ -337,7 +351,7 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu
 ;     -- Registered Output Connections                        ; 0                   ; 0                              ;
 ;                                                             ;                     ;                                ;
 ; Internal Connections                                        ;                     ;                                ;
-;     -- Total Connections                                    ; 60                  ; 0                              ;
+;     -- Total Connections                                    ; 99                  ; 0                              ;
 ;     -- Registered Connections                               ; 0                   ; 0                              ;
 ;                                                             ;                     ;                                ;
 ; External Connections                                        ;                     ;                                ;
@@ -345,8 +359,8 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu
 ;     -- hard_block:auto_generated_inst                       ; 0                   ; 0                              ;
 ;                                                             ;                     ;                                ;
 ; Partition Interface                                         ;                     ;                                ;
-;     -- Input Ports                                          ; 5                   ; 0                              ;
-;     -- Output Ports                                         ; 8                   ; 0                              ;
+;     -- Input Ports                                          ; 8                   ; 0                              ;
+;     -- Output Ports                                         ; 16                  ; 0                              ;
 ;     -- Bidir Ports                                          ; 0                   ; 0                              ;
 ;                                                             ;                     ;                                ;
 ; Registered Ports                                            ;                     ;                                ;
@@ -365,33 +379,44 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu
 +-------------------------------------------------------------+---------------------+--------------------------------+
 
 
-+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
 ; Input Pins                                                                                                                                                                                                                                                                          ;
-+------------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+----------+--------------+--------------+-------------+---------------------------+----------------------+-----------+
++------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+----------+--------------+--------------+-------------+---------------------------+----------------------+-----------+
 ; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination ; Termination Control Block ; Location assigned by ; Slew Rate ;
-+------------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+----------+--------------+--------------+-------------+---------------------------+----------------------+-----------+
-; num[0]     ; AC9   ; 3B       ; 14           ; 0            ; 34           ; 8                     ; 0                  ; no     ; no             ; no              ; no       ; Off          ; 2.5 V        ; Off         ; --                        ; User                 ; no        ;
-; num[1]     ; AE10  ; 4A       ; 36           ; 0            ; 51           ; 8                     ; 0                  ; no     ; no             ; no              ; no       ; Off          ; 2.5 V        ; Off         ; --                        ; User                 ; no        ;
-; num[2]     ; AD13  ; 4A       ; 34           ; 0            ; 34           ; 8                     ; 0                  ; no     ; no             ; no              ; no       ; Off          ; 2.5 V        ; Off         ; --                        ; User                 ; no        ;
-; num[3]     ; AC8   ; 3B       ; 14           ; 0            ; 51           ; 8                     ; 0                  ; no     ; no             ; no              ; no       ; Off          ; 2.5 V        ; Off         ; --                        ; User                 ; no        ;
-; rbi_inv[0] ; AE19  ; 4A       ; 50           ; 0            ; 34           ; 7                     ; 0                  ; no     ; no             ; no              ; no       ; Off          ; 2.5 V        ; Off         ; --                        ; User                 ; no        ;
-+------------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+----------+--------------+--------------+-------------+---------------------------+----------------------+-----------+
++------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+----------+--------------+--------------+-------------+---------------------------+----------------------+-----------+
+; a[0] ; AC9   ; 3B       ; 14           ; 0            ; 34           ; 7                     ; 0                  ; no     ; no             ; no              ; no       ; Off          ; 1.2 V        ; Off         ; --                        ; User                 ; no        ;
+; a[1] ; AE10  ; 4A       ; 36           ; 0            ; 51           ; 7                     ; 0                  ; no     ; no             ; no              ; no       ; Off          ; 1.2 V        ; Off         ; --                        ; User                 ; no        ;
+; a[2] ; AD13  ; 4A       ; 34           ; 0            ; 34           ; 7                     ; 0                  ; no     ; no             ; no              ; no       ; Off          ; 1.2 V        ; Off         ; --                        ; User                 ; no        ;
+; a[3] ; AC8   ; 3B       ; 14           ; 0            ; 51           ; 7                     ; 0                  ; no     ; no             ; no              ; no       ; Off          ; 1.2 V        ; Off         ; --                        ; User                 ; no        ;
+; b[0] ; W11   ; 3B       ; 10           ; 0            ; 40           ; 8                     ; 0                  ; no     ; no             ; no              ; no       ; Off          ; 1.2 V        ; Off         ; --                        ; User                 ; no        ;
+; b[1] ; AB10  ; 3B       ; 12           ; 0            ; 34           ; 8                     ; 0                  ; no     ; no             ; no              ; no       ; Off          ; 1.2 V        ; Off         ; --                        ; User                 ; no        ;
+; b[2] ; V10   ; 3B       ; 17           ; 0            ; 74           ; 8                     ; 0                  ; no     ; no             ; no              ; no       ; Off          ; 1.2 V        ; Off         ; --                        ; User                 ; no        ;
+; b[3] ; AC10  ; 3B       ; 12           ; 0            ; 51           ; 8                     ; 0                  ; no     ; no             ; no              ; no       ; Off          ; 1.2 V        ; Off         ; --                        ; User                 ; no        ;
++------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+----------+--------------+--------------+-------------+---------------------------+----------------------+-----------+
 
 
-+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
 ; Output Pins                                                                                                                                                                                                                                                                                                                                                                                                                                                                                   ;
-+-------------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+---------------------+-----------------------------+----------------------+----------------------+---------------------+
++----------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+---------------------+-----------------------------+----------------------+----------------------+---------------------+
 ; Name     ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Output Register ; Output Enable Register ; Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination                       ; Termination Control Block ; Output Buffer Pre-emphasis ; Voltage Output Differential ; Output Buffer Delay ; Output Buffer Delay Control ; Location assigned by ; Output Enable Source ; Output Enable Group ;
-+-------------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+---------------------+-----------------------------+----------------------+----------------------+---------------------+
-; segments[0] ; F7    ; 8A       ; 14           ; 61           ; 51           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
-; segments[1] ; V19   ; 4A       ; 66           ; 0            ; 0            ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
-; segments[2] ; V18   ; 4A       ; 64           ; 0            ; 0            ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
-; segments[3] ; V17   ; 4A       ; 64           ; 0            ; 17           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
-; segments[4] ; W18   ; 4A       ; 66           ; 0            ; 17           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
-; segments[5] ; Y20   ; 4A       ; 65           ; 0            ; 0            ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
-; segments[6] ; Y19   ; 4A       ; 65           ; 0            ; 17           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
-; segments[7] ; Y18   ; 4A       ; 62           ; 0            ; 40           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
-+-------------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+---------------------+-----------------------------+----------------------+----------------------+---------------------+
++----------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+---------------------+-----------------------------+----------------------+----------------------+---------------------+
+; seg_a[0] ; G12   ; 7A       ; 36           ; 61           ; 0            ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 1.2 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; 0                   ; Off                         ; Fitter               ; -                    ; -                   ;
+; seg_a[1] ; V19   ; 4A       ; 66           ; 0            ; 0            ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 1.2 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; seg_a[2] ; V18   ; 4A       ; 64           ; 0            ; 0            ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 1.2 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; seg_a[3] ; V17   ; 4A       ; 64           ; 0            ; 17           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 1.2 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; seg_a[4] ; W18   ; 4A       ; 66           ; 0            ; 17           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 1.2 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; seg_a[5] ; Y20   ; 4A       ; 65           ; 0            ; 0            ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 1.2 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; seg_a[6] ; Y19   ; 4A       ; 65           ; 0            ; 17           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 1.2 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; seg_a[7] ; Y18   ; 4A       ; 62           ; 0            ; 40           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 1.2 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; seg_b[0] ; AD21  ; 4A       ; 57           ; 0            ; 51           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 1.2 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; 0                   ; Off                         ; Fitter               ; -                    ; -                   ;
+; seg_b[1] ; AA18  ; 4A       ; 62           ; 0            ; 57           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 1.2 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; seg_b[2] ; AD26  ; 4A       ; 64           ; 0            ; 34           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 1.2 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; seg_b[3] ; AB19  ; 4A       ; 65           ; 0            ; 34           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 1.2 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; seg_b[4] ; AE26  ; 4A       ; 64           ; 0            ; 51           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 1.2 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; seg_b[5] ; AE25  ; 4A       ; 62           ; 0            ; 74           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 1.2 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; seg_b[6] ; AC19  ; 4A       ; 65           ; 0            ; 51           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 1.2 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; seg_b[7] ; AF24  ; 4A       ; 62           ; 0            ; 91           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 1.2 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
++----------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+---------------------+-----------------------------+----------------------+----------------------+---------------------+
 
 
 +----------------------------------------------------------------------------+
@@ -402,13 +427,13 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu
 ; B1L      ; 0 / 14 ( 0 % )   ; --            ; --           ; --            ;
 ; B0L      ; 0 / 14 ( 0 % )   ; --            ; --           ; --            ;
 ; 3A       ; 0 / 16 ( 0 % )   ; 2.5V          ; --           ; 2.5V          ;
-; 3B       ; 2 / 32 ( 6 % )   ; 2.5V          ; --           ; 2.5V          ;
-; 4A       ; 10 / 80 ( 13 % ) ; 2.5V          ; --           ; 2.5V          ;
+; 3B       ; 6 / 32 ( 19 % )  ; 1.2V          ; --           ; 2.5V          ;
+; 4A       ; 17 / 80 ( 21 % ) ; 1.2V          ; --           ; 2.5V          ;
 ; 5A       ; 0 / 16 ( 0 % )   ; 2.5V          ; --           ; 2.5V          ;
 ; 5B       ; 0 / 32 ( 0 % )   ; 2.5V          ; --           ; 2.5V          ;
 ; 6A       ; 0 / 48 ( 0 % )   ; 2.5V          ; --           ; 2.5V          ;
-; 7A       ; 0 / 80 ( 0 % )   ; 2.5V          ; --           ; 2.5V          ;
-; 8A       ; 1 / 32 ( 3 % )   ; 2.5V          ; --           ; 2.5V          ;
+; 7A       ; 1 / 80 ( 1 % )   ; 1.2V          ; --           ; 2.5V          ;
+; 8A       ; 0 / 32 ( 0 % )   ; 2.5V          ; --           ; 2.5V          ;
 +----------+------------------+---------------+--------------+---------------+
 
 
@@ -425,7 +450,7 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu
 ; A7       ; 348        ; 8A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
 ; A8       ; 308        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
 ; A9       ; 310        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; A10      ;            ; 7A       ; VCCIO7A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; A10      ;            ; 7A       ; VCCIO7A                         ; power  ;              ; 1.2V                ; --           ;                 ; --       ; --           ;
 ; A11      ; 322        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
 ; A12      ; 332        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
 ; A13      ; 330        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
@@ -435,7 +460,7 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu
 ; A17      ; 292        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
 ; A18      ; 290        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
 ; A19      ; 288        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; A20      ;            ; 7A       ; VCCIO7A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; A20      ;            ; 7A       ; VCCIO7A                         ; power  ;              ; 1.2V                ; --           ;                 ; --       ; --           ;
 ; A21      ; 274        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
 ; A22      ; 270        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
 ; A23      ; 268        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
@@ -450,7 +475,7 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu
 ; AA7      ; 47         ; 3A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
 ; AA8      ;            ; --       ; VCC_AUX                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
 ; AA9      ;            ; --       ; VCCPGM                          ; power  ;              ; 1.8V/2.5V/3.0V/3.3V ; --           ;                 ; --       ; --           ;
-; AA10     ;            ; 3B       ; VCCIO3B                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; AA10     ;            ; 3B       ; VCCIO3B                         ; power  ;              ; 1.2V                ; --           ;                 ; --       ; --           ;
 ; AA11     ;            ; 3B, 4A   ; VCCPD3B4A                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
 ; AA12     ;            ;          ; NC                              ;        ;              ;                     ; --           ;                 ; --       ; --           ;
 ; AA13     ;            ; 3B, 4A   ; VCCPD3B4A                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
@@ -458,9 +483,9 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu
 ; AA15     ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
 ; AA16     ; 113        ; 4A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
 ; AA17     ;            ; 3B, 4A   ; VCCPD3B4A                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; AA18     ; 151        ; 4A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AA18     ; 151        ; 4A       ; seg_b[1]                        ; output ; 1.2 V        ;                     ; Column I/O   ; Y               ; no       ; Off          ;
 ; AA19     ;            ; 3B, 4A   ; VCCPD3B4A                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; AA20     ;            ; 4A       ; VCCIO4A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; AA20     ;            ; 4A       ; VCCIO4A                         ; power  ;              ; 1.2V                ; --           ;                 ; --       ; --           ;
 ; AA21     ; 163        ; 4A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
 ; AA22     ; 170        ; 5A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
 ; AA23     ; 172        ; 5A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
@@ -476,16 +501,16 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu
 ; AB7      ;            ;          ; NC                              ;        ;              ;                     ; --           ;                 ; --       ; --           ;
 ; AB8      ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
 ; AB9      ;            ; 3A       ; VCCPD3A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; AB10     ; 61         ; 3B       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AB10     ; 61         ; 3B       ; b[1]                            ; input  ; 1.2 V        ;                     ; Column I/O   ; Y               ; no       ; Off          ;
 ; AB11     ; 63         ; 3B       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
 ; AB12     ; 65         ; 3B       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AB13     ;            ; 4A       ; VCCIO4A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; AB13     ;            ; 4A       ; VCCIO4A                         ; power  ;              ; 1.2V                ; --           ;                 ; --       ; --           ;
 ; AB14     ;            ; --       ; VCC_AUX                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
 ; AB15     ; 105        ; 4A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
 ; AB16     ; 111        ; 4A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
 ; AB17     ; 129        ; 4A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
 ; AB18     ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; AB19     ; 160        ; 4A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AB19     ; 160        ; 4A       ; seg_b[3]                        ; output ; 1.2 V        ;                     ; Column I/O   ; Y               ; no       ; Off          ;
 ; AB20     ;            ; --       ; VCC_AUX                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
 ; AB21     ;            ; 3B, 4A   ; VCCPD3B4A                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
 ; AB22     ; 165        ; 4A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
@@ -500,18 +525,18 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu
 ; AC5      ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
 ; AC6      ;            ; 3A       ; VCCIO3A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
 ; AC7      ;            ; 3A       ; VREFB3AN0                       ; power  ;              ;                     ; --           ;                 ; --       ; --           ;
-; AC8      ; 62         ; 3B       ; num[3]                          ; input  ; 2.5 V        ;                     ; Column I/O   ; Y               ; no       ; Off          ;
-; AC9      ; 64         ; 3B       ; num[0]                          ; input  ; 2.5 V        ;                     ; Column I/O   ; Y               ; no       ; Off          ;
-; AC10     ; 59         ; 3B       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AC8      ; 62         ; 3B       ; a[3]                            ; input  ; 1.2 V        ;                     ; Column I/O   ; Y               ; no       ; Off          ;
+; AC9      ; 64         ; 3B       ; a[0]                            ; input  ; 1.2 V        ;                     ; Column I/O   ; Y               ; no       ; Off          ;
+; AC10     ; 59         ; 3B       ; b[3]                            ; input  ; 1.2 V        ;                     ; Column I/O   ; Y               ; no       ; Off          ;
 ; AC11     ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
 ; AC12     ;            ; 3B       ; VREFB3BN0                       ; power  ;              ;                     ; --           ;                 ; --       ; --           ;
 ; AC13     ; 102        ; 4A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
 ; AC14     ; 104        ; 4A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
 ; AC15     ; 103        ; 4A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AC16     ;            ; 4A       ; VCCIO4A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; AC16     ;            ; 4A       ; VCCIO4A                         ; power  ;              ; 1.2V                ; --           ;                 ; --       ; --           ;
 ; AC17     ; 127        ; 4A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
 ; AC18     ; 120        ; 4A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AC19     ; 158        ; 4A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AC19     ; 158        ; 4A       ; seg_b[6]                        ; output ; 1.2 V        ;                     ; Column I/O   ; Y               ; no       ; Off          ;
 ; AC20     ; 136        ; 4A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
 ; AC21     ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
 ; AC22     ; 166        ; 5A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
@@ -527,24 +552,24 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu
 ; AD6      ; 51         ; 3A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
 ; AD7      ; 53         ; 3A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
 ; AD8      ; 73         ; 3B       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AD9      ;            ; 3B       ; VCCIO3B                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; AD9      ;            ; 3B       ; VCCIO3B                         ; power  ;              ; 1.2V                ; --           ;                 ; --       ; --           ;
 ; AD10     ; 96         ; 4A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
 ; AD11     ; 88         ; 4A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
 ; AD12     ; 91         ; 4A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AD13     ; 93         ; 4A       ; num[2]                          ; input  ; 2.5 V        ;                     ; Column I/O   ; Y               ; no       ; Off          ;
+; AD13     ; 93         ; 4A       ; a[2]                            ; input  ; 1.2 V        ;                     ; Column I/O   ; Y               ; no       ; Off          ;
 ; AD14     ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
 ; AD15     ;            ; 4A       ; VREFB4AN0                       ; power  ;              ;                     ; --           ;                 ; --       ; --           ;
 ; AD16     ; 119        ; 4A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
 ; AD17     ; 121        ; 4A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
 ; AD18     ; 118        ; 4A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AD19     ;            ; 4A       ; VCCIO4A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; AD19     ;            ; 4A       ; VCCIO4A                         ; power  ;              ; 1.2V                ; --           ;                 ; --       ; --           ;
 ; AD20     ; 134        ; 4A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AD21     ; 139        ; 4A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AD21     ; 139        ; 4A       ; seg_b[0]                        ; output ; 1.2 V        ;                     ; Column I/O   ; N               ; no       ; Off          ;
 ; AD22     ; 141        ; 4A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
 ; AD23     ; 144        ; 4A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
 ; AD24     ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
 ; AD25     ; 191        ; 5B       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; AD26     ; 157        ; 4A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AD26     ; 157        ; 4A       ; seg_b[2]                        ; output ; 1.2 V        ;                     ; Column I/O   ; Y               ; no       ; Off          ;
 ; AE1      ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
 ; AE2      ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
 ; AE3      ; 22         ; B0L      ; GXB_NC                          ;        ;              ;                     ; --           ;                 ; --       ; --           ;
@@ -554,23 +579,23 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu
 ; AE7      ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
 ; AE8      ; 71         ; 3B       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
 ; AE9      ; 77         ; 3B       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AE10     ; 94         ; 4A       ; num[1]                          ; input  ; 2.5 V        ;                     ; Column I/O   ; Y               ; no       ; Off          ;
+; AE10     ; 94         ; 4A       ; a[1]                            ; input  ; 1.2 V        ;                     ; Column I/O   ; Y               ; no       ; Off          ;
 ; AE11     ; 86         ; 4A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AE12     ;            ; 4A       ; VCCIO4A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; AE12     ;            ; 4A       ; VCCIO4A                         ; power  ;              ; 1.2V                ; --           ;                 ; --       ; --           ;
 ; AE13     ; 109        ; 4A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
 ; AE14     ; 112        ; 4A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
 ; AE15     ; 135        ; 4A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
 ; AE16     ; 137        ; 4A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
 ; AE17     ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
 ; AE18     ; 117        ; 4A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AE19     ; 125        ; 4A       ; rbi_inv[0]                      ; input  ; 2.5 V        ;                     ; Column I/O   ; Y               ; no       ; Off          ;
+; AE19     ; 125        ; 4A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
 ; AE20     ; 133        ; 4A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
 ; AE21     ; 131        ; 4A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AE22     ;            ; 4A       ; VCCIO4A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; AE22     ;            ; 4A       ; VCCIO4A                         ; power  ;              ; 1.2V                ; --           ;                 ; --       ; --           ;
 ; AE23     ; 142        ; 4A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
 ; AE24     ; 149        ; 4A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AE25     ; 152        ; 4A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AE26     ; 155        ; 4A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AE25     ; 152        ; 4A       ; seg_b[5]                        ; output ; 1.2 V        ;                     ; Column I/O   ; Y               ; no       ; Off          ;
+; AE26     ; 155        ; 4A       ; seg_b[4]                        ; output ; 1.2 V        ;                     ; Column I/O   ; Y               ; no       ; Off          ;
 ; AF2      ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
 ; AF3      ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
 ; AF4      ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
@@ -584,7 +609,7 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu
 ; AF12     ; 99         ; 4A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
 ; AF13     ; 107        ; 4A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
 ; AF14     ; 110        ; 4A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AF15     ;            ; 4A       ; VCCIO4A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; AF15     ;            ; 4A       ; VCCIO4A                         ; power  ;              ; 1.2V                ; --           ;                 ; --       ; --           ;
 ; AF16     ; 143        ; 4A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
 ; AF17     ; 145        ; 4A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
 ; AF18     ; 115        ; 4A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
@@ -593,7 +618,7 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu
 ; AF21     ; 128        ; 4A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
 ; AF22     ; 126        ; 4A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
 ; AF23     ; 147        ; 4A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AF24     ; 150        ; 4A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AF24     ; 150        ; 4A       ; seg_b[7]                        ; output ; 1.2 V        ;                     ; Column I/O   ; Y               ; no       ; Off          ;
 ; AF25     ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
 ; B1       ;            ;          ; RREF                            ;        ;              ;                     ; --           ;                 ; --       ; --           ;
 ; B2       ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
@@ -607,7 +632,7 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu
 ; B10      ; 320        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
 ; B11      ; 334        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
 ; B12      ; 328        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; B13      ;            ; 7A       ; VCCIO7A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; B13      ;            ; 7A       ; VCCIO7A                         ; power  ;              ; 1.2V                ; --           ;                 ; --       ; --           ;
 ; B14      ; 302        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
 ; B15      ; 304        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
 ; B16      ;            ; 7A       ; VREFB7AN0                       ; power  ;              ;                     ; --           ;                 ; --       ; --           ;
@@ -617,7 +642,7 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu
 ; B20      ; 278        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
 ; B21      ; 276        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
 ; B22      ; 272        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; B23      ;            ; 7A       ; VCCIO7A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; B23      ;            ; 7A       ; VCCIO7A                         ; power  ;              ; 1.2V                ; --           ;                 ; --       ; --           ;
 ; B24      ; 267        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
 ; B25      ; 247        ; 6A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
 ; B26      ; 249        ; 6A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
@@ -636,7 +661,7 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu
 ; C13      ; 336        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
 ; C14      ; 307        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
 ; C15      ; 306        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; C16      ;            ; 7A       ; VCCIO7A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; C16      ;            ; 7A       ; VCCIO7A                         ; power  ;              ; 1.2V                ; --           ;                 ; --       ; --           ;
 ; C17      ; 296        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
 ; C18      ; 286        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
 ; C19      ; 284        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
@@ -665,7 +690,7 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu
 ; D16      ; 317        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
 ; D17      ; 293        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
 ; D18      ; 291        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; D19      ;            ; 7A       ; VCCIO7A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; D19      ;            ; 7A       ; VCCIO7A                         ; power  ;              ; 1.2V                ; --           ;                 ; --       ; --           ;
 ; D20      ; 277        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
 ; D21      ; 275        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
 ; D22      ; 255        ; 6A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
@@ -684,7 +709,7 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu
 ; E9       ; 374        ; 8A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
 ; E10      ; 324        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
 ; E11      ; 326        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; E12      ;            ; 7A       ; VCCIO7A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; E12      ;            ; 7A       ; VCCIO7A                         ; power  ;              ; 1.2V                ; --           ;                 ; --       ; --           ;
 ; E13      ; 339        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
 ; E14      ;            ; --       ; VCC_AUX                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
 ; E15      ; 325        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
@@ -705,7 +730,7 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu
 ; F4       ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
 ; F5       ; 398        ; 9A       ; ^nCONFIG                        ;        ;              ;                     ; --           ;                 ; --       ; --           ;
 ; F6       ; 360        ; 8A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; F7       ; 366        ; 8A       ; segments[0]                     ; output ; 2.5 V        ;                     ; Column I/O   ; Y               ; no       ; Off          ;
+; F7       ; 366        ; 8A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
 ; F8       ;            ; --       ; VCCPGM                          ; power  ;              ; 1.8V/2.5V/3.0V/3.3V ; --           ;                 ; --       ; --           ;
 ; F9       ;            ; 7A, 8A   ; VCCPD7A8A                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
 ; F10      ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
@@ -713,7 +738,7 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu
 ; F12      ; 333        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
 ; F13      ;            ; 7A, 8A   ; VCCPD7A8A                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
 ; F14      ;            ;          ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
-; F15      ;            ; 7A       ; VCCIO7A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; F15      ;            ; 7A       ; VCCIO7A                         ; power  ;              ; 1.2V                ; --           ;                 ; --       ; --           ;
 ; F16      ; 323        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
 ; F17      ;            ; 7A, 8A   ; VCCPD7A8A                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
 ; F18      ; 301        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
@@ -736,13 +761,13 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu
 ; G9       ;            ; --       ; VCC_AUX                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
 ; G10      ; 357        ; 8A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
 ; G11      ; 329        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; G12      ; 331        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; G12      ; 331        ; 7A       ; seg_a[0]                        ; output ; 1.2 V        ;                     ; Column I/O   ; N               ; no       ; Off          ;
 ; G13      ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
 ; G14      ; 313        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
 ; G15      ; 311        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
 ; G16      ; 279        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
 ; G17      ; 281        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; G18      ;            ; 7A       ; VCCIO7A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; G18      ;            ; 7A       ; VCCIO7A                         ; power  ;              ; 1.2V                ; --           ;                 ; --       ; --           ;
 ; G19      ;            ; --       ; VCC_AUX                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
 ; G20      ; 258        ; 6A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
 ; G21      ;            ; --       ; VCCA_FPLL                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
@@ -761,7 +786,7 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu
 ; H8       ; 347        ; 8A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
 ; H9       ; 349        ; 8A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
 ; H10      ; 355        ; 8A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; H11      ;            ; 7A       ; VCCIO7A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; H11      ;            ; 7A       ; VCCIO7A                         ; power  ;              ; 1.2V                ; --           ;                 ; --       ; --           ;
 ; H12      ; 327        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
 ; H13      ; 297        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
 ; H14      ; 295        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
@@ -992,7 +1017,7 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu
 ; U5       ;            ; --       ; VCCE_GXBL                       ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
 ; U6       ; 31         ; 3A       ; ^AS_DATA3, DATA3                ;        ;              ;                     ; Weak Pull Up ;                 ; --       ; On           ;
 ; U7       ; 39         ; 3A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; U8       ;            ; 3B       ; VCCIO3B                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; U8       ;            ; 3B       ; VCCIO3B                         ; power  ;              ; 1.2V                ; --           ;                 ; --       ; --           ;
 ; U9       ; 54         ; 3B       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
 ; U10      ; 81         ; 3B       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
 ; U11      ; 79         ; 3B       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
@@ -1002,7 +1027,7 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu
 ; U15      ; 148        ; 4A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
 ; U16      ; 146        ; 4A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
 ; U17      ; 130        ; 4A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; U18      ;            ; 4A       ; VCCIO4A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; U18      ;            ; 4A       ; VCCIO4A                         ; power  ;              ; 1.2V                ; --           ;                 ; --       ; --           ;
 ; U19      ; 167        ; 5A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
 ; U20      ; 181        ; 5A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
 ; U21      ;            ; 5A       ; VCCPD5A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
@@ -1020,16 +1045,16 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu
 ; V7       ; 28         ; 3A       ; #TDO                            ; output ;              ;                     ; --           ;                 ; --       ; --           ;
 ; V8       ; 41         ; 3A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
 ; V9       ; 70         ; 3B       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; V10      ; 72         ; 3B       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; V11      ;            ; 3B       ; VCCIO3B                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; V10      ; 72         ; 3B       ; b[2]                            ; input  ; 1.2 V        ;                     ; Column I/O   ; Y               ; no       ; Off          ;
+; V11      ;            ; 3B       ; VCCIO3B                         ; power  ;              ; 1.2V                ; --           ;                 ; --       ; --           ;
 ; V12      ; 98         ; 4A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
 ; V13      ; 92         ; 4A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
 ; V14      ; 106        ; 4A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
 ; V15      ; 124        ; 4A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
 ; V16      ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; V17      ; 154        ; 4A       ; segments[3]                     ; output ; 2.5 V        ;                     ; Column I/O   ; Y               ; no       ; Off          ;
-; V18      ; 156        ; 4A       ; segments[2]                     ; output ; 2.5 V        ;                     ; Column I/O   ; Y               ; no       ; Off          ;
-; V19      ; 164        ; 4A       ; segments[1]                     ; output ; 2.5 V        ;                     ; Column I/O   ; Y               ; no       ; Off          ;
+; V17      ; 154        ; 4A       ; seg_a[3]                        ; output ; 1.2 V        ;                     ; Column I/O   ; Y               ; no       ; Off          ;
+; V18      ; 156        ; 4A       ; seg_a[2]                        ; output ; 1.2 V        ;                     ; Column I/O   ; Y               ; no       ; Off          ;
+; V19      ; 164        ; 4A       ; seg_a[1]                        ; output ; 1.2 V        ;                     ; Column I/O   ; Y               ; no       ; Off          ;
 ; V20      ; 169        ; 5A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
 ; V21      ;            ; 5A       ; VCCIO5A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
 ; V22      ; 175        ; 5A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
@@ -1047,14 +1072,14 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu
 ; W8       ; 42         ; 3A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
 ; W9       ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
 ; W10      ; 69         ; 3B       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; W11      ; 57         ; 3B       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; W11      ; 57         ; 3B       ; b[0]                            ; input  ; 1.2 V        ;                     ; Column I/O   ; Y               ; no       ; Off          ;
 ; W12      ; 97         ; 4A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
 ; W13      ; 90         ; 4A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; W14      ;            ; 4A       ; VCCIO4A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; W14      ;            ; 4A       ; VCCIO4A                         ; power  ;              ; 1.2V                ; --           ;                 ; --       ; --           ;
 ; W15      ; 122        ; 4A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
 ; W16      ; 140        ; 4A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
 ; W17      ; 138        ; 4A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; W18      ; 162        ; 4A       ; segments[4]                     ; output ; 2.5 V        ;                     ; Column I/O   ; Y               ; no       ; Off          ;
+; W18      ; 162        ; 4A       ; seg_a[4]                        ; output ; 1.2 V        ;                     ; Column I/O   ; Y               ; no       ; Off          ;
 ; W19      ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
 ; W20      ; 171        ; 5A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
 ; W21      ; 173        ; 5A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
@@ -1079,10 +1104,10 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu
 ; Y14      ; 89         ; 4A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
 ; Y15      ; 116        ; 4A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
 ; Y16      ; 114        ; 4A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; Y17      ;            ; 4A       ; VCCIO4A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; Y18      ; 153        ; 4A       ; segments[7]                     ; output ; 2.5 V        ;                     ; Column I/O   ; Y               ; no       ; Off          ;
-; Y19      ; 159        ; 4A       ; segments[6]                     ; output ; 2.5 V        ;                     ; Column I/O   ; Y               ; no       ; Off          ;
-; Y20      ; 161        ; 4A       ; segments[5]                     ; output ; 2.5 V        ;                     ; Column I/O   ; Y               ; no       ; Off          ;
+; Y17      ;            ; 4A       ; VCCIO4A                         ; power  ;              ; 1.2V                ; --           ;                 ; --       ; --           ;
+; Y18      ; 153        ; 4A       ; seg_a[7]                        ; output ; 1.2 V        ;                     ; Column I/O   ; Y               ; no       ; Off          ;
+; Y19      ; 159        ; 4A       ; seg_a[6]                        ; output ; 1.2 V        ;                     ; Column I/O   ; Y               ; no       ; Off          ;
+; Y20      ; 161        ; 4A       ; seg_a[5]                        ; output ; 1.2 V        ;                     ; Column I/O   ; Y               ; no       ; Off          ;
 ; Y21      ;            ; --       ; VCCA_FPLL                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
 ; Y22      ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
 ; Y23      ; 178        ; 5A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
@@ -1093,108 +1118,150 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu
 Note: Pin directions (input, output or bidir) are based on device operating in user mode.
 
 
-+---------------------------------------------+
++-------------------------------------------------+
 ; I/O Assignment Warnings                         ;
-+-------------+-------------------------------+
++----------+--------------------------------------+
 ; Pin Name ; Reason                               ;
-+-------------+-------------------------------+
-; segments[0] ; Incomplete set of assignments ;
-; segments[1] ; Incomplete set of assignments ;
-; segments[2] ; Incomplete set of assignments ;
-; segments[3] ; Incomplete set of assignments ;
-; segments[4] ; Incomplete set of assignments ;
-; segments[5] ; Incomplete set of assignments ;
-; segments[6] ; Incomplete set of assignments ;
-; segments[7] ; Incomplete set of assignments ;
-; num[0]      ; Incomplete set of assignments ;
-; rbi_inv[0]  ; Incomplete set of assignments ;
-; num[3]      ; Incomplete set of assignments ;
-; num[1]      ; Incomplete set of assignments ;
-; num[2]      ; Incomplete set of assignments ;
-+-------------+-------------------------------+
++----------+--------------------------------------+
+; seg_b[0] ; Missing drive strength and slew rate ;
+; seg_b[1] ; Missing drive strength and slew rate ;
+; seg_b[2] ; Missing drive strength and slew rate ;
+; seg_b[3] ; Missing drive strength and slew rate ;
+; seg_b[4] ; Missing drive strength and slew rate ;
+; seg_b[5] ; Missing drive strength and slew rate ;
+; seg_b[6] ; Missing drive strength and slew rate ;
+; seg_b[7] ; Missing drive strength and slew rate ;
+; seg_a[0] ; Missing drive strength and slew rate ;
+; seg_a[1] ; Missing drive strength and slew rate ;
+; seg_a[2] ; Missing drive strength and slew rate ;
+; seg_a[3] ; Missing drive strength and slew rate ;
+; seg_a[4] ; Missing drive strength and slew rate ;
+; seg_a[5] ; Missing drive strength and slew rate ;
+; seg_a[6] ; Missing drive strength and slew rate ;
+; seg_a[7] ; Missing drive strength and slew rate ;
+; seg_b[0] ; Missing location assignment          ;
+; seg_a[0] ; Missing location assignment          ;
++----------+--------------------------------------+
 
 
-+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
 ; Fitter Resource Utilization by Entity                                                                                                                                                                                                                                                                                                                                                                           ;
-+----------------------------+----------------------+----------------------------------+---------------------------------------------------+----------------------------------+----------------------+---------------------+---------------------------+---------------+-------------------+-------+------------+------+--------------+---------------------+-------------+--------------+
++----------------------------+----------------------+----------------------------------+---------------------------------------------------+----------------------------------+----------------------+---------------------+---------------------------+---------------+-------------------+-------+------------+------+--------------+-----------------------------------------+------------------+--------------+
 ; Compilation Hierarchy Node ; ALMs needed [=A-B+C] ; [A] ALMs used in final placement ; [B] Estimate of ALMs recoverable by dense packing ; [C] Estimate of ALMs unavailable ; ALMs used for memory ; Combinational ALUTs ; Dedicated Logic Registers ; I/O Registers ; Block Memory Bits ; M10Ks ; DSP Blocks ; Pins ; Virtual Pins ; Full Hierarchy Name                     ; Entity Name      ; Library Name ;
-+----------------------------+----------------------+----------------------------------+---------------------------------------------------+----------------------------------+----------------------+---------------------+---------------------------+---------------+-------------------+-------+------------+------+--------------+---------------------+-------------+--------------+
-; |seven_seg                 ; 4.5 (4.5)            ; 8.0 (8.0)                        ; 3.5 (3.5)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 9 (9)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 13   ; 0            ; |seven_seg          ; seven_seg   ; work         ;
-+----------------------------+----------------------+----------------------------------+---------------------------------------------------+----------------------------------+----------------------+---------------------+---------------------------+---------------+-------------------+-------+------------+------+--------------+---------------------+-------------+--------------+
++----------------------------+----------------------+----------------------------------+---------------------------------------------------+----------------------------------+----------------------+---------------------+---------------------------+---------------+-------------------+-------+------------+------+--------------+-----------------------------------------+------------------+--------------+
+; |seven_seg_2digit          ; 8.0 (0.5)            ; 8.0 (0.5)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 16 (1)              ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 24   ; 0            ; |seven_seg_2digit                       ; seven_seg_2digit ; work         ;
+;    |seven_seg:left_digit|  ; 4.0 (4.0)            ; 4.0 (4.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 8 (8)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |seven_seg_2digit|seven_seg:left_digit  ; seven_seg        ; work         ;
+;    |seven_seg:right_digit| ; 3.5 (3.5)            ; 3.5 (3.5)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 7 (7)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |seven_seg_2digit|seven_seg:right_digit ; seven_seg        ; work         ;
++----------------------------+----------------------+----------------------------------+---------------------------------------------------+----------------------------------+----------------------+---------------------+---------------------------+---------------+-------------------+-------+------------+------+--------------+-----------------------------------------+------------------+--------------+
 Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
 
 
-+----------------------------------------------------------------------------------------------------------------------------+
++-------------------------------------------------------------------------------------------------------------------------+
 ; Delay Chain Summary                                                                                                     ;
-+-------------+----------+----+------+------+----+------+-------+--------+------------------------+--------------------------+
++----------+----------+----+------+------+----+------+-------+--------+------------------------+--------------------------+
 ; Name     ; Pin Type ; D1 ; D3_0 ; D3_1 ; D4 ; D5   ; D5 OE ; D5 OCT ; T11 (Postamble Gating) ; T11 (Postamble Ungating) ;
-+-------------+----------+----+------+------+----+------+-------+--------+------------------------+--------------------------+
-; segments[0] ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
-; segments[1] ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
-; segments[2] ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
-; segments[3] ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
-; segments[4] ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
-; segments[5] ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
-; segments[6] ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
-; segments[7] ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
-; num[0]      ; Input    ; -- ; (0)  ; --   ; -- ; --   ; --    ; --     ; --                     ; --                       ;
-; rbi_inv[0]  ; Input    ; -- ; (0)  ; --   ; -- ; --   ; --    ; --     ; --                     ; --                       ;
-; num[3]      ; Input    ; -- ; --   ; (0)  ; -- ; --   ; --    ; --     ; --                     ; --                       ;
-; num[1]      ; Input    ; -- ; --   ; (0)  ; -- ; --   ; --    ; --     ; --                     ; --                       ;
-; num[2]      ; Input    ; -- ; --   ; (0)  ; -- ; --   ; --    ; --     ; --                     ; --                       ;
-+-------------+----------+----+------+------+----+------+-------+--------+------------------------+--------------------------+
++----------+----------+----+------+------+----+------+-------+--------+------------------------+--------------------------+
+; seg_b[0] ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; seg_b[1] ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; seg_b[2] ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; seg_b[3] ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; seg_b[4] ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; seg_b[5] ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; seg_b[6] ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; seg_b[7] ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; seg_a[0] ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; seg_a[1] ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; seg_a[2] ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; seg_a[3] ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; seg_a[4] ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; seg_a[5] ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; seg_a[6] ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; seg_a[7] ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; b[0]     ; Input    ; -- ; --   ; (0)  ; -- ; --   ; --    ; --     ; --                     ; --                       ;
+; b[1]     ; Input    ; -- ; (0)  ; --   ; -- ; --   ; --    ; --     ; --                     ; --                       ;
+; b[2]     ; Input    ; -- ; (0)  ; --   ; -- ; --   ; --    ; --     ; --                     ; --                       ;
+; b[3]     ; Input    ; -- ; --   ; (0)  ; -- ; --   ; --    ; --     ; --                     ; --                       ;
+; a[0]     ; Input    ; -- ; (0)  ; --   ; -- ; --   ; --    ; --     ; --                     ; --                       ;
+; a[1]     ; Input    ; -- ; --   ; (0)  ; -- ; --   ; --    ; --     ; --                     ; --                       ;
+; a[2]     ; Input    ; -- ; --   ; (0)  ; -- ; --   ; --    ; --     ; --                     ; --                       ;
+; a[3]     ; Input    ; -- ; --   ; (0)  ; -- ; --   ; --    ; --     ; --                     ; --                       ;
++----------+----------+----+------+------+----+------+-------+--------+------------------------+--------------------------+
 
 
-+---------------------------------------------------+
++----------------------------------------------------------------------+
 ; Pad To Core Delay Chain Fanout                                       ;
-+---------------------+-------------------+---------+
++----------------------------------------+-------------------+---------+
 ; Source Pin / Fanout                    ; Pad To Core Index ; Setting ;
-+---------------------+-------------------+---------+
-; num[0]              ;                   ;         ;
-;      - segments~0   ; 0                 ; 0       ;
-;      - Mux5~0       ; 0                 ; 0       ;
-;      - Mux4~0       ; 0                 ; 0       ;
-;      - Mux3~0       ; 0                 ; 0       ;
-;      - Mux2~0       ; 0                 ; 0       ;
-;      - Mux1~0       ; 0                 ; 0       ;
-;      - Mux0~0       ; 0                 ; 0       ;
-;      - WideOr0~0    ; 0                 ; 0       ;
-; rbi_inv[0]          ;                   ;         ;
-;      - segments~0   ; 0                 ; 0       ;
-;      - Mux5~0       ; 0                 ; 0       ;
-;      - Mux4~0       ; 0                 ; 0       ;
-;      - Mux3~0       ; 0                 ; 0       ;
-;      - Mux2~0       ; 0                 ; 0       ;
-;      - Mux1~0       ; 0                 ; 0       ;
-;      - Mux0~0       ; 0                 ; 0       ;
-; num[3]              ;                   ;         ;
-;      - segments~0   ; 1                 ; 0       ;
-;      - Mux5~0       ; 1                 ; 0       ;
-;      - Mux4~0       ; 1                 ; 0       ;
-;      - Mux3~0       ; 1                 ; 0       ;
-;      - Mux2~0       ; 1                 ; 0       ;
-;      - Mux1~0       ; 1                 ; 0       ;
-;      - Mux0~0       ; 1                 ; 0       ;
-;      - WideOr0~0    ; 1                 ; 0       ;
-; num[1]              ;                   ;         ;
-;      - segments~0   ; 1                 ; 0       ;
-;      - Mux5~0       ; 1                 ; 0       ;
-;      - Mux4~0       ; 1                 ; 0       ;
-;      - Mux3~0       ; 1                 ; 0       ;
-;      - Mux2~0       ; 1                 ; 0       ;
-;      - Mux1~0       ; 1                 ; 0       ;
-;      - Mux0~0       ; 1                 ; 0       ;
-;      - WideOr0~0    ; 1                 ; 0       ;
-; num[2]              ;                   ;         ;
-;      - segments~0   ; 1                 ; 0       ;
-;      - Mux5~0       ; 1                 ; 0       ;
-;      - Mux4~0       ; 1                 ; 0       ;
-;      - Mux3~0       ; 1                 ; 0       ;
-;      - Mux2~0       ; 1                 ; 0       ;
-;      - Mux1~0       ; 1                 ; 0       ;
-;      - Mux0~0       ; 1                 ; 0       ;
-;      - WideOr0~0    ; 1                 ; 0       ;
-+---------------------+-------------------+---------+
++----------------------------------------+-------------------+---------+
+; b[0]                                   ;                   ;         ;
+;      - seven_seg:left_digit|Decoder0~0 ; 1                 ; 0       ;
+;      - seven_seg:left_digit|Mux5~0     ; 1                 ; 0       ;
+;      - seven_seg:left_digit|Mux4~0     ; 1                 ; 0       ;
+;      - seven_seg:left_digit|Mux3~0     ; 1                 ; 0       ;
+;      - seven_seg:left_digit|Mux2~0     ; 1                 ; 0       ;
+;      - seven_seg:left_digit|Mux1~0     ; 1                 ; 0       ;
+;      - seven_seg:left_digit|Mux0~0     ; 1                 ; 0       ;
+;      - seven_seg:left_digit|WideOr0~0  ; 1                 ; 0       ;
+; b[1]                                   ;                   ;         ;
+;      - seven_seg:left_digit|Decoder0~0 ; 0                 ; 0       ;
+;      - seven_seg:left_digit|Mux5~0     ; 0                 ; 0       ;
+;      - seven_seg:left_digit|Mux4~0     ; 0                 ; 0       ;
+;      - seven_seg:left_digit|Mux3~0     ; 0                 ; 0       ;
+;      - seven_seg:left_digit|Mux2~0     ; 0                 ; 0       ;
+;      - seven_seg:left_digit|Mux1~0     ; 0                 ; 0       ;
+;      - seven_seg:left_digit|Mux0~0     ; 0                 ; 0       ;
+;      - seven_seg:left_digit|WideOr0~0  ; 0                 ; 0       ;
+; b[2]                                   ;                   ;         ;
+;      - seven_seg:left_digit|Decoder0~0 ; 0                 ; 0       ;
+;      - seven_seg:left_digit|Mux5~0     ; 0                 ; 0       ;
+;      - seven_seg:left_digit|Mux4~0     ; 0                 ; 0       ;
+;      - seven_seg:left_digit|Mux3~0     ; 0                 ; 0       ;
+;      - seven_seg:left_digit|Mux2~0     ; 0                 ; 0       ;
+;      - seven_seg:left_digit|Mux1~0     ; 0                 ; 0       ;
+;      - seven_seg:left_digit|Mux0~0     ; 0                 ; 0       ;
+;      - seven_seg:left_digit|WideOr0~0  ; 0                 ; 0       ;
+; b[3]                                   ;                   ;         ;
+;      - seven_seg:left_digit|Decoder0~0 ; 1                 ; 0       ;
+;      - seven_seg:left_digit|Mux5~0     ; 1                 ; 0       ;
+;      - seven_seg:left_digit|Mux4~0     ; 1                 ; 0       ;
+;      - seven_seg:left_digit|Mux3~0     ; 1                 ; 0       ;
+;      - seven_seg:left_digit|Mux2~0     ; 1                 ; 0       ;
+;      - seven_seg:left_digit|Mux1~0     ; 1                 ; 0       ;
+;      - seven_seg:left_digit|Mux0~0     ; 1                 ; 0       ;
+;      - seven_seg:left_digit|WideOr0~0  ; 1                 ; 0       ;
+; a[0]                                   ;                   ;         ;
+;      - seven_seg:right_digit|Mux5~0    ; 0                 ; 0       ;
+;      - seven_seg:right_digit|Mux4~0    ; 0                 ; 0       ;
+;      - seven_seg:right_digit|Mux3~0    ; 0                 ; 0       ;
+;      - seven_seg:right_digit|Mux2~0    ; 0                 ; 0       ;
+;      - seven_seg:right_digit|Mux1~0    ; 0                 ; 0       ;
+;      - seven_seg:right_digit|Mux0~0    ; 0                 ; 0       ;
+;      - seven_seg:right_digit|WideOr0~0 ; 0                 ; 0       ;
+; a[1]                                   ;                   ;         ;
+;      - seven_seg:right_digit|Mux5~0    ; 1                 ; 0       ;
+;      - seven_seg:right_digit|Mux4~0    ; 1                 ; 0       ;
+;      - seven_seg:right_digit|Mux3~0    ; 1                 ; 0       ;
+;      - seven_seg:right_digit|Mux2~0    ; 1                 ; 0       ;
+;      - seven_seg:right_digit|Mux1~0    ; 1                 ; 0       ;
+;      - seven_seg:right_digit|Mux0~0    ; 1                 ; 0       ;
+;      - seven_seg:right_digit|WideOr0~0 ; 1                 ; 0       ;
+; a[2]                                   ;                   ;         ;
+;      - seven_seg:right_digit|Mux5~0    ; 1                 ; 0       ;
+;      - seven_seg:right_digit|Mux4~0    ; 1                 ; 0       ;
+;      - seven_seg:right_digit|Mux3~0    ; 1                 ; 0       ;
+;      - seven_seg:right_digit|Mux2~0    ; 1                 ; 0       ;
+;      - seven_seg:right_digit|Mux1~0    ; 1                 ; 0       ;
+;      - seven_seg:right_digit|Mux0~0    ; 1                 ; 0       ;
+;      - seven_seg:right_digit|WideOr0~0 ; 1                 ; 0       ;
+; a[3]                                   ;                   ;         ;
+;      - seven_seg:right_digit|Mux5~0    ; 1                 ; 0       ;
+;      - seven_seg:right_digit|Mux4~0    ; 1                 ; 0       ;
+;      - seven_seg:right_digit|Mux3~0    ; 1                 ; 0       ;
+;      - seven_seg:right_digit|Mux2~0    ; 1                 ; 0       ;
+;      - seven_seg:right_digit|Mux1~0    ; 1                 ; 0       ;
+;      - seven_seg:right_digit|Mux0~0    ; 1                 ; 0       ;
+;      - seven_seg:right_digit|WideOr0~0 ; 1                 ; 0       ;
++----------------------------------------+-------------------+---------+
 
 
 +-------------------------------------------------------+
@@ -1202,10 +1269,10 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
 +------------------------------+------------------------+
 ; Routing Resource Type        ; Usage                  ;
 +------------------------------+------------------------+
-; Block interconnects          ; 13 / 217,884 ( < 1 % ) ;
-; C12 interconnects            ; 0 / 10,080 ( 0 % )     ;
-; C2 interconnects             ; 10 / 87,208 ( < 1 % )  ;
-; C4 interconnects             ; 17 / 41,360 ( < 1 % )  ;
+; Block interconnects          ; 23 / 217,884 ( < 1 % ) ;
+; C12 interconnects            ; 4 / 10,080 ( < 1 % )   ;
+; C2 interconnects             ; 14 / 87,208 ( < 1 % )  ;
+; C4 interconnects             ; 7 / 41,360 ( < 1 % )   ;
 ; DQS bus muxes                ; 0 / 21 ( 0 % )         ;
 ; DQS-18 I/O buses             ; 0 / 21 ( 0 % )         ;
 ; DQS-9 I/O buses              ; 0 / 21 ( 0 % )         ;
@@ -1214,10 +1281,10 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
 ; Horizontal periphery clocks  ; 0 / 12 ( 0 % )         ;
 ; Local interconnects          ; 0 / 58,160 ( 0 % )     ;
 ; Quadrant clocks              ; 0 / 88 ( 0 % )         ;
-; R14 interconnects            ; 10 / 9,228 ( < 1 % )   ;
-; R14/C12 interconnect drivers ; 10 / 15,096 ( < 1 % )  ;
-; R3 interconnects             ; 13 / 94,896 ( < 1 % )  ;
-; R6 interconnects             ; 19 / 194,640 ( < 1 % ) ;
+; R14 interconnects            ; 19 / 9,228 ( < 1 % )   ;
+; R14/C12 interconnect drivers ; 19 / 15,096 ( < 1 % )  ;
+; R3 interconnects             ; 27 / 94,896 ( < 1 % )  ;
+; R6 interconnects             ; 14 / 194,640 ( < 1 % ) ;
 ; Spine clocks                 ; 0 / 180 ( 0 % )        ;
 ; Wire stub REs                ; 0 / 11,606 ( 0 % )     ;
 +------------------------------+------------------------+
@@ -1273,29 +1340,40 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
 +--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+
 
 
-+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
 ; I/O Rules Matrix                                                                                                                                                                                                                                                                                                                                                                                                                              ;
-+--------------------+--------------+-----------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+-----------+--------------+
++--------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+-----------+--------------+
 ; Pin/Rules          ; IO_000002    ; IO_000001    ; IO_000003    ; IO_000004    ; IO_000005    ; IO_000006 ; IO_000007    ; IO_000008    ; IO_000047    ; IO_000046    ; IO_000045    ; IO_000027    ; IO_000026    ; IO_000024    ; IO_000023    ; IO_000022    ; IO_000021    ; IO_000020    ; IO_000019    ; IO_000018    ; IO_000015    ; IO_000014    ; IO_000013    ; IO_000012    ; IO_000011    ; IO_000010 ; IO_000009 ; IO_000034    ;
-+--------------------+--------------+-----------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+-----------+--------------+
-; Total Pass         ; 0            ; 13        ; 13        ; 0            ; 0            ; 13        ; 13        ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 8            ; 0            ; 0            ; 0            ; 0            ; 8            ; 0            ; 0            ; 0            ; 0            ; 8            ; 0            ; 13        ; 13        ; 0            ;
++--------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+-----------+--------------+
+; Total Pass         ; 0            ; 22           ; 22           ; 0            ; 0            ; 24        ; 22           ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 16           ; 0            ; 0            ; 0            ; 0            ; 16           ; 0            ; 0            ; 0            ; 0            ; 16           ; 0            ; 24        ; 24        ; 0            ;
 ; Total Unchecked    ; 0            ; 0            ; 0            ; 0            ; 0            ; 0         ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0         ; 0         ; 0            ;
-; Total Inapplicable ; 13           ; 0         ; 0         ; 13           ; 13           ; 0         ; 0         ; 13           ; 13           ; 13           ; 13           ; 13           ; 13           ; 5            ; 13           ; 13           ; 13           ; 13           ; 5            ; 13           ; 13           ; 13           ; 13           ; 5            ; 13           ; 0         ; 0         ; 13           ;
+; Total Inapplicable ; 24           ; 2            ; 2            ; 24           ; 24           ; 0         ; 2            ; 24           ; 24           ; 24           ; 24           ; 24           ; 24           ; 8            ; 24           ; 24           ; 24           ; 24           ; 8            ; 24           ; 24           ; 24           ; 24           ; 8            ; 24           ; 0         ; 0         ; 24           ;
 ; Total Fail         ; 0            ; 0            ; 0            ; 0            ; 0            ; 0         ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0         ; 0         ; 0            ;
-; segments[0]        ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ;
-; segments[1]        ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ;
-; segments[2]        ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ;
-; segments[3]        ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ;
-; segments[4]        ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ;
-; segments[5]        ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ;
-; segments[6]        ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ;
-; segments[7]        ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ;
-; num[0]             ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ;
-; rbi_inv[0]         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ;
-; num[3]             ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ;
-; num[1]             ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ;
-; num[2]             ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ;
-+--------------------+--------------+-----------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+-----------+--------------+
+; seg_b[0]           ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ;
+; seg_b[1]           ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ;
+; seg_b[2]           ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ;
+; seg_b[3]           ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ;
+; seg_b[4]           ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ;
+; seg_b[5]           ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ;
+; seg_b[6]           ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ;
+; seg_b[7]           ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ;
+; seg_a[0]           ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ;
+; seg_a[1]           ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ;
+; seg_a[2]           ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ;
+; seg_a[3]           ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ;
+; seg_a[4]           ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ;
+; seg_a[5]           ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ;
+; seg_a[6]           ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ;
+; seg_a[7]           ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ;
+; b[0]               ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ;
+; b[1]               ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ;
+; b[2]               ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ;
+; b[3]               ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ;
+; a[0]               ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ;
+; a[1]               ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ;
+; a[2]               ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ;
+; a[3]               ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ;
++--------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+-----------+--------------+
 
 
 +------------------------------------------------------------------------------------------------+
@@ -1352,11 +1430,14 @@ Info (21077): High junction temperature is 85 degrees C
 Info (171003): Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
 Warning (292013): Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature.
 Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details
+Critical Warning (169085): No exact pin location assignment(s) for 2 pins of 24 total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report.
 Info (184020): Starting Fitter periphery placement operations
 Info (184021): Fitter periphery placement operations ending: elapsed time is 00:00:00
 Info (176233): Starting register packing
 Info (176235): Finished register packing
     Extra Info (176219): No registers were packed into other blocks
+Warning (15705): Ignored locations or region assignments to the following nodes
+    Warning (15706): Node "rbi[0]" is assigned to location or region, but does not exist in design
 Info (11798): Fitter preparation operations ending: elapsed time is 00:00:07
 Critical Warning (332012): Synopsys Design Constraints File file not found: 'seven_seg.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
 Info (332144): No user constrained base clocks found in the design
@@ -1373,7 +1454,7 @@ Info (170137): Fitter placement was successful
 Info (170192): Fitter placement operations ending: elapsed time is 00:00:00
 Info (170193): Fitter routing operations beginning
 Info (170195): Router estimated average interconnect usage is 0% of the available device resources
-    Info (170196): Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X46_Y0 to location X56_Y11
+    Info (170196): Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X57_Y0 to location X68_Y11
 Info (170199): The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time.
     Info (170201): Optimizations that may affect the design's routability were skipped
     Info (170200): Optimizations that may affect the design's timing were skipped
@@ -1384,10 +1465,11 @@ Info (334004): Delay annotation completed successfully
 Info (334003): Started post-fitting delay annotation
 Info (334004): Delay annotation completed successfully
 Info (11801): Fitter post-fit operations ending: elapsed time is 00:00:04
-Info: Quartus Prime Fitter was successful. 0 errors, 5 warnings
-    Info: Peak virtual memory: 1384 megabytes
-    Info: Processing ended: Thu Sep  3 16:57:35 2026
-    Info: Elapsed time: 00:00:27
-    Info: Total CPU time (on all processors): 00:00:39
+Warning (171167): Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information.
+Info: Quartus Prime Fitter was successful. 0 errors, 9 warnings
+    Info: Peak virtual memory: 1392 megabytes
+    Info: Processing ended: Tue Sep 15 21:07:03 2026
+    Info: Elapsed time: 00:00:29
+    Info: Total CPU time (on all processors): 00:00:41
 
 

Quartus/A1_Q1/output_files/seven_seg.fit.smsg

@@ -0,0 +1,6 @@
+Extra Info (176236): Started Fast Input/Output/OE register processing
+Extra Info (176237): Finished Fast Input/Output/OE register processing
+Extra Info (176238): Start inferring scan chains for DSP blocks
+Extra Info (176239): Inferring scan chains for DSP blocks is complete
+Extra Info (176246): Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density
+Extra Info (176247): Finished moving registers into I/O cells, DSP blocks, and RAM blocks

Quartus/A1_Q1/output_files/seven_seg.fit.summary

@@ -1,13 +1,13 @@
-Fitter Status : Successful - Thu Sep  3 16:57:35 2026
+Fitter Status : Successful - Tue Sep 15 21:07:03 2026
 Quartus Prime Version : 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
 Revision Name : seven_seg
-Top-level Entity Name : seven_seg
+Top-level Entity Name : seven_seg_2digit
 Family : Cyclone V
 Device : 5CGXFC5C6F27C7
 Timing Models : Final
-Logic utilization (in ALMs) : 5 / 29,080 ( < 1 % )
+Logic utilization (in ALMs) : 8 / 29,080 ( < 1 % )
 Total registers : 0
-Total pins : 13 / 364 ( 4 % )
+Total pins : 24 / 364 ( 7 % )
 Total virtual pins : 0
 Total block memory bits : 0 / 4,567,040 ( 0 % )
 Total RAM Blocks : 0 / 446 ( 0 % )

Quartus/A1_Q1/output_files/seven_seg.flow.rpt

@@ -1,5 +1,5 @@
 Flow report for seven_seg
-Thu Sep  3 16:57:51 2026
+Tue Sep 15 21:07:19 2026
 Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
 
 
@@ -41,16 +41,16 @@ on the Quartus Prime software download page.
 +-----------------------------------------------------------------------------------+
 ; Flow Summary                                                                      ;
 +---------------------------------+-------------------------------------------------+
-; Flow Status                     ; Successful - Thu Sep  3 16:57:51 2026           ;
+; Flow Status                     ; Successful - Tue Sep 15 21:07:19 2026           ;
 ; Quartus Prime Version           ; 25.1std.0 Build 1129 10/21/2025 SC Lite Edition ;
 ; Revision Name                   ; seven_seg                                       ;
-; Top-level Entity Name           ; seven_seg                                       ;
+; Top-level Entity Name           ; seven_seg_2digit                                ;
 ; Family                          ; Cyclone V                                       ;
 ; Device                          ; 5CGXFC5C6F27C7                                  ;
 ; Timing Models                   ; Final                                           ;
-; Logic utilization (in ALMs)     ; 5 / 29,080 ( < 1 % )                            ;
+; Logic utilization (in ALMs)     ; 8 / 29,080 ( < 1 % )                            ;
 ; Total registers                 ; 0                                               ;
-; Total pins                      ; 13 / 364 ( 4 % )                                ;
+; Total pins                      ; 24 / 364 ( 7 % )                                ;
 ; Total virtual pins              ; 0                                               ;
 ; Total block memory bits         ; 0 / 4,567,040 ( 0 % )                           ;
 ; Total DSP Blocks                ; 0 / 150 ( 0 % )                                 ;
@@ -68,18 +68,18 @@ on the Quartus Prime software download page.
 +-------------------+---------------------+
 ; Option            ; Setting             ;
 +-------------------+---------------------+
-; Start date & time ; 09/03/2026 16:56:55 ;
+; Start date & time ; 09/15/2026 21:06:22 ;
 ; Main task         ; Compilation         ;
 ; Revision Name     ; seven_seg           ;
 +-------------------+---------------------+
 
 
-+------------------------------------------------------------------------------------------------------------------------------------------------+
++-----------------------------------------------------------------------------------------------------------------------------------------------------+
 ; Flow Non-Default Global Settings                                                                                                                    ;
-+-------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+
++-------------------------------------+----------------------------------------+---------------+------------------+-----------------------------------+
 ; Assignment Name                     ; Value                                  ; Default Value ; Entity Name      ; Section Id                        ;
-+-------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+
-; COMPILER_SIGNATURE_ID               ; 55629860311554.178841861509729         ; --            ; --          ; --                                ;
++-------------------------------------+----------------------------------------+---------------+------------------+-----------------------------------+
+; COMPILER_SIGNATURE_ID               ; 268883478169649.178947038213924        ; --            ; --               ; --                                ;
 ; EDA_GENERATE_FUNCTIONAL_NETLIST     ; Off                                    ; --            ; --               ; eda_board_design_timing           ;
 ; EDA_GENERATE_FUNCTIONAL_NETLIST     ; Off                                    ; --            ; --               ; eda_board_design_boundary_scan    ;
 ; EDA_GENERATE_FUNCTIONAL_NETLIST     ; Off                                    ; --            ; --               ; eda_board_design_signal_integrity ;
@@ -89,11 +89,14 @@ on the Quartus Prime software download page.
 ; EDA_TIME_SCALE                      ; 1 ps                                   ; --            ; --               ; eda_simulation                    ;
 ; MAX_CORE_JUNCTION_TEMP              ; 85                                     ; --            ; --               ; --                                ;
 ; MIN_CORE_JUNCTION_TEMP              ; 0                                      ; --            ; --               ; --                                ;
-; PARTITION_COLOR                     ; -- (Not supported for targeted family) ; --            ; --          ; Top                               ;
-; PARTITION_FITTER_PRESERVATION_LEVEL ; -- (Not supported for targeted family) ; --            ; --          ; Top                               ;
-; PARTITION_NETLIST_TYPE              ; -- (Not supported for targeted family) ; --            ; --          ; Top                               ;
+; PARTITION_COLOR                     ; -- (Not supported for targeted family) ; --            ; seven_seg_2digit ; Top                               ;
+; PARTITION_FITTER_PRESERVATION_LEVEL ; -- (Not supported for targeted family) ; --            ; seven_seg_2digit ; Top                               ;
+; PARTITION_NETLIST_TYPE              ; -- (Not supported for targeted family) ; --            ; seven_seg_2digit ; Top                               ;
+; POWER_BOARD_THERMAL_MODEL           ; None (CONSERVATIVE)                    ; --            ; --               ; --                                ;
+; POWER_PRESET_COOLING_SOLUTION       ; 23 MM HEAT SINK WITH 200 LFPM AIRFLOW  ; --            ; --               ; --                                ;
 ; PROJECT_OUTPUT_DIRECTORY            ; output_files                           ; --            ; --               ; --                                ;
-+-------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+
+; TOP_LEVEL_ENTITY                    ; seven_seg_2digit                       ; seven_seg     ; --               ; --                                ;
++-------------------------------------+----------------------------------------+---------------+------------------+-----------------------------------+
 
 
 +--------------------------------------------------------------------------------------------------------------------------+
@@ -101,12 +104,12 @@ on the Quartus Prime software download page.
 +----------------------+--------------+-------------------------+---------------------+------------------------------------+
 ; Module Name          ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
 +----------------------+--------------+-------------------------+---------------------+------------------------------------+
-; Analysis & Synthesis ; 00:00:11     ; 1.0                     ; 419 MB              ; 00:00:27                           ;
-; Fitter               ; 00:00:27     ; 1.0                     ; 1384 MB             ; 00:00:38                           ;
-; Assembler            ; 00:00:05     ; 1.0                     ; 525 MB              ; 00:00:05                           ;
-; Timing Analyzer      ; 00:00:06     ; 1.0                     ; 780 MB              ; 00:00:05                           ;
-; EDA Netlist Writer   ; 00:00:01     ; 1.0                     ; 658 MB              ; 00:00:01                           ;
-; Total                ; 00:00:50     ; --                      ; --                  ; 00:01:16                           ;
+; Analysis & Synthesis ; 00:00:10     ; 1.0                     ; 422 MB              ; 00:00:24                           ;
+; Fitter               ; 00:00:29     ; 1.0                     ; 1392 MB             ; 00:00:41                           ;
+; Assembler            ; 00:00:05     ; 1.0                     ; 514 MB              ; 00:00:05                           ;
+; Timing Analyzer      ; 00:00:06     ; 1.0                     ; 769 MB              ; 00:00:06                           ;
+; EDA Netlist Writer   ; 00:00:01     ; 1.0                     ; 670 MB              ; 00:00:01                           ;
+; Total                ; 00:00:51     ; --                      ; --                  ; 00:01:17                           ;
 +----------------------+--------------+-------------------------+---------------------+------------------------------------+