TroubleElectrical/FPGA_Uni
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c894488c44025a9105fef5d2d9884713a4b4ed04
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91 Commits
Author SHA1 Message Date
TroubleElectrical c894488c44 Fixed ByteIM.sv and removed seven seg from A3 code 2026-11-05 14:33:41 +11:00
riley 74a15cf038 Made ROM binary file configurable via a parameter. Updated assignment2 and assignment3 to reflect this. Added bit slicing in assignment2 for ram/rom addresses. 2026-11-05 14:27:01 +11:00
riley 38fa35fccd Fixed initialisation bug and compilation error in gatereg module. Added mips_pipelined to test suite. Fixed several bugs in assignment3 MIPS module 2026-11-05 14:10:13 +11:00
riley cc98bfbf02 Fixed compile error caused by trailing comma 2026-11-05 12:25:01 +11:00
riley f8ea90e41d Created assignment 3 MIPS module that uses pipelining 2026-11-04 17:28:36 +11:00
riley 8f9ec010ac Updated gate register module to support arbitary delays to prevent littering uper-level code with gatereg->gatereg logic values. 2026-11-04 15:40:25 +11:00
riley b046ad7db0 Created register for gating pipeline stage results 2026-10-29 15:34:31 +11:00
TroubleElectrical 8b48084fa5 Repaired Sign extender module again to ensure only combinational logic used 
(There was a compilation error before, also compiled and tested code on board)
 2026-10-22 15:53:15 +11:00
riley 5eb78e92e9 Fixed bugs in sign extender 2026-10-20 16:14:02 +11:00
riley 9648db6e77 Switched to used boolean && rather than bitwise & in sign extender 2026-10-20 16:02:14 +11:00
riley a647305bd9 Fixed bug where ram datawidth was not 2^N. 2026-10-20 16:01:34 +11:00
TroubleElectrical d962a1b557 Added code to display current PC, 
Removed Blanking from 7seg 4 digits,
Changed reset to a switch rather than button
Compiled working version for board
 2026-10-16 14:27:29 +11:00
riley 59f7f372f6 Fixed bug where ASU intermediate was being treated as the overflow flag rather than an intermediate. 2026-10-16 12:33:04 +11:00
riley e7fff9f3dc Added explicit rst input to RAM and PC as well as the MIPS processor. 2026-10-16 12:11:19 +11:00
riley c717bf189c Added comment to document the zero-flag 2026-10-16 11:57:55 +11:00
riley 5ae9125e06 Fixed a couple bugs introduced from merge-conflict resolution 2026-10-16 11:50:07 +11:00
riley 8a682347f0 Merge branch 'main' of ssh://git.rileyk.au:19482/TroubleElectrical/FPGA_Uni 2026-10-16 11:44:03 +11:00
riley 92a0cb17da Updated assignment 2 to reflect prior changes. Fixed instruction ordering for register file module (again). Fixed typo that limited the space the ALU could write its flags out to. Swapped ordering to be correct when determining if we are storing the result from ALU or MEM. 
Added a QUARTUS_SYNTH around the display logic at the end of the module.
Partially fixed control_unit module, still seems to need some changes as branching doesn't appear to work at all.
 2026-10-16 11:38:35 +11:00
riley 65be2c2d61 Made sign extension explicit to remove bit indexing (which iverilog doesn't like) and a tad more readable. 2026-10-16 11:35:24 +11:00
riley 878f949e5f Made addrwidth sizing consistent with the 2^N used everywhere 2026-10-16 11:34:31 +11:00
riley 0ea3e0fa12 Added initialisation blocks for PC and GPR's 2026-10-16 11:33:45 +11:00
TroubleElectrical 5d9e7f541e Updated RAM code to make sure Bus width is 32 bits 2026-10-16 11:32:47 +11:00
riley 12ae58ad86 Removed flag assignment from within ALU OP case statement and instead perform it at the end. Made bit index for the ASU OP more explicit. 2026-10-16 11:32:24 +11:00
riley 4c7e2ff085 Fixed instruction width issue in ROM. Stripped all comments to form minimal HEX file to rule out possible parser issues. 2026-10-16 11:29:04 +11:00
riley a63d46bc77 Merge branch 'main' of ssh://git.rileyk.au:19482/TroubleElectrical/FPGA_Uni 2026-10-15 15:54:38 +11:00
riley 04d1d3e2fe Added control unit. TODO: Test 2026-10-15 15:53:59 +11:00
TroubleElectrical cdde70e6c2 Updated ram.sv to resolve compilation error 2026-10-15 15:42:26 +11:00
TroubleElectrical cd7fecd1c4 Updated code such that it will compile 2026-10-15 15:32:15 +11:00
riley 5fc24f7859 Temp change to make RAM word-aligned 2026-10-15 15:28:27 +11:00
riley 2e042fbd93 Merge branch 'main' of ssh://git.rileyk.au:19482/TroubleElectrical/FPGA_Uni 2026-10-15 15:18:09 +11:00
riley a336df9d80 Reworked CPU to use control unit 2026-10-15 15:16:57 +11:00
TroubleElectrical afb6fefe1b Updated Assignment2 with better register file module insantiation 2026-10-15 15:07:41 +11:00
TroubleElectrical 10bf499065 Merge branch 'main' of ssh://git.rileyk.au:19482/TroubleElectrical/FPGA_Uni 2026-10-15 14:52:14 +11:00
TroubleElectrical 8c6765eb83 Updated reg file and assignment for compilation 2026-10-15 14:49:32 +11:00
riley 1c93c082ae Merge branch 'main' of ssh://git.rileyk.au:19482/TroubleElectrical/FPGA_Uni 2026-10-15 14:48:06 +11:00
riley d9f44f93df Halfway added imm,branch and mem ops 2026-10-15 14:46:51 +11:00
TroubleElectrical ac1062fbd5 Added Register Display Code 2026-10-15 14:35:10 +11:00
TroubleElectrical 81c05b6531 Merge branch 'main' of ssh://git.rileyk.au:19482/TroubleElectrical/FPGA_Uni 2026-10-15 14:27:48 +11:00
TroubleElectrical 6bb6368f6c Added external register inspection code 2026-10-15 14:23:38 +11:00
riley 25ed477df9 Rewrote ternary operator to be less confusing 2026-10-15 14:04:36 +11:00
riley 1e13de9301 Updated assignment2. Created file for testing R-type instructions, still needs to be implemented. Consider using bind to be able to extract inner-scoped variables out for inspection. 2026-10-13 22:26:52 +11:00
riley ac6c4cc094 Added module for sign extension. Needs test cases 2026-10-13 22:24:43 +11:00
riley 75ef513efa Added zero flag to ALU and updated testbench to not fail because of it. TODO: Add cases to test the zero flag 2026-10-13 21:34:25 +11:00
TroubleElectrical 25a953cdc6 Added 4 digit 7seg display module (confirmed working for now), 
Added Inputs for displaying registers / Program Counter high and low bits,
Assigned pins for Display digits, inputs (Labeled HID) and the clk button
 2026-10-13 16:32:15 +11:00
TroubleElectrical 353923eadf Updated Assignment to remove ../../ includes (unnesccesary, also SYNTHESIS macro is not used by quartus, so I manually have QUARTUS_SYNTH for those includes) 2026-10-13 15:12:00 +11:00
TroubleElectrical 19b07b649d Repaired last few errors in modules and ensured compilation with QUARTUS_BUILD global flag in Quartus build settings and compiled fully (no errors other than pin assignments) 2026-10-13 13:24:44 +11:00
riley f91fe0681a Fixed parameter ordering in instancing 2026-10-13 12:45:15 +11:00
riley a04d6b92cb Updated register file to use 2^n rather than n 2026-10-13 12:43:53 +11:00
riley ba9ab863d8 Fixed ordering for instruction counter and added module output gating for writing 2026-10-13 12:33:24 +11:00
riley 6d731b5a6b Merge branch 'main' of ssh://git.rileyk.au:19482/TroubleElectrical/FPGA_Uni 2026-10-13 12:29:52 +11:00