Merge branch 'main' of ssh://git.rileyk.au:19482/TroubleElectrical/FPGA_Uni

modules/assignment2.sv

@@ -1,11 +1,26 @@
-`include "rom.sv"
-`include "ram.sv"
-`include "register_file.sv"
-`include "instruction_counter.sv"
-`include "instruction_classifier.sv"
-`include "instruction_module_classifier.sv"
-`include "alu.sv"
-`include "shifter.sv"
+`ifndef ASS_2_SV
+`define ASS_2_SV
+
+`ifdef SYNTHESIS
+	`include "../../rom.sv"
+    `include "../../ram.sv"
+    `include "../../register_file.sv"
+    `include "../../instruction_counter.sv"
+    `include "../../instruction_classifier.sv"
+    `include "../../instruction_module_classifier.sv"
+    `include "../../alu.sv"
+    `include "../../shifter.sv"
+`else
+	`include "rom.sv"
+    `include "ram.sv"
+    `include "register_file.sv"
+    `include "instruction_counter.sv"
+    `include "instruction_classifier.sv"
+    `include "instruction_module_classifier.sv"
+    `include "alu.sv"
+    `include "shifter.sv"
+`endif
+
 
 
 module assignment2 #(width=5, ramsz=9, romsz=10) (input logic [0:0] clk);
@@ -50,4 +65,6 @@ module assignment2 #(width=5, ramsz=9, romsz=10) (input logic [0:0] clk);
     logic [2**width-1:0] rd_shifter;
     shifter SHIFTER #(width)(instruction[2:0], rt, rs[4:0], instruction[10:6], rd_shifter);
     
-endmodule
+endmodule
+
+`endif

modules/assignment2.sv.bak

@@ -0,0 +1,19 @@
+`include "rom.sv"
+`include "ram.sv"
+`include "instruction_counter.sv"
+`include "instruction_classifier.sv"
+`include "alu.sv"
+
+
+module assignment2 #(width=5, ramsz=9, romsz=10) (input logic [0:0] clk);
+    
+    logic [romsz-1:0] pc_addr;
+    logic [0:0] pc_we;
+    logic [2**width-1:0] instruction;
+
+    instruction_counter pc #(romsz)(clk, pc_we, pc_addr, pc_addr);
+    ROM rom #(romsz, 2**width)();
+    RAM ram #(ramsz,  2**width)();
+    alu alu #(width)();
+
+endmodule

modules/instruction_counter.sv

@@ -8,14 +8,14 @@ module instruction_counter #(parameter width=5)(
 );
 
     logic [2**width-1:0] pc;
-    always_ff (@posedge clk) begin
+    always_ff @(posedge clk) begin
         if (we) begin
-            pc <= W
-        else
+            pc <= W;
+        end else begin
             pc <= pc + 4;
         end
     end
 
     assign addr = pc;
 endmodule
-`endif
+`endif

modules/ram.sv

@@ -1,4 +1,7 @@
-module rom #(addrwidth=9, datawidth=5)(
+`ifndef RAM_H
+`define RAM_H
+
+module ram #(addrwidth=9, datawidth=5)(
     input logic [0:0] clk,
     input logic [2**addrwidth-1:0] addr,
     input logic [0:0] we,
@@ -15,11 +18,13 @@ module rom #(addrwidth=9, datawidth=5)(
         end
     end
 
-    always_ff(@posedge clk) begin
+    always_ff @(posedge clk) begin
         if (we) begin
             mem[addr] <= data_in;
         end
     end
     assign data_out = mem[addr];
 
-endmodule;
+endmodule
+
+`endif

modules/rom.sv

@@ -1,3 +1,5 @@
+`ifndef ROM_H
+`define ROM_H
 
 module rom #(parameter m=7,p=4) (
         input logic [m-1:0] Ad,
@@ -17,3 +19,5 @@ module rom #(parameter m=7,p=4) (
         `endif
     end
 endmodule // end rom module
+
+`endif