TroubleElectrical 81c05b6531 Merge branch 'main' of ssh://git.rileyk.au:19482/TroubleElectrical/FPGA_Uni

2026-10-15 14:27:48 +11:00

..

alu.sv

Added zero flag to ALU and updated testbench to not fail because of it. TODO: Add cases to test the zero flag

2026-10-13 21:34:25 +11:00

alu.sv.bak

Updated ALU code with updated 2**width approach and assigned temporary pins to ASU (Q3)

2026-09-09 14:27:11 +10:00

assignment2.sv

Updated assignment2. Created file for testing R-type instructions, still needs to be implemented. Consider using bind to be able to extract inner-scoped variables out for inspection.

2026-10-13 22:26:52 +11:00

assignment2.sv.bak

Updated assignment 2 dependency modules (currently 8 errors in compile)

2026-10-13 12:23:52 +11:00

asu.sv

Removed seven segment code from alu and asu

2026-09-24 15:37:48 +10:00

asu.sv.bak

Added ModelSim folder (and have to add files into it as to allow for different testbench code)

2026-09-08 16:32:01 +10:00

ByteIM.sv

Added Byte addressable ROM from Slides

2026-10-06 16:28:23 +11:00

instruction_classifier.sv

Updated instruction classifier to use combinational logic with a depth of 3 gates (AND, XNOR, HAND)

2026-09-13 23:35:05 +10:00

instruction_counter.sv

Updated assignment 2 dependency modules (currently 8 errors in compile)

2026-10-13 12:23:52 +11:00

instruction_module_classifier.sv

Repaired last few errors in modules and ensured compilation with QUARTUS_BUILD global flag in Quartus build settings and compiled fully (no errors other than pin assignments)

2026-10-13 13:24:44 +11:00

lu.sv

Added comments to Logic Unit (Q2) and added to submission file

2026-09-16 12:38:06 +10:00

lu.sv.bak

Updated Q2 project and LU code such that it operates properly on the board. Changed to utilising a case statement for easier readability and also compiled and tested the code on the board.

2026-09-08 15:36:51 +10:00

ram.sv

Updated assignment 2 dependency modules (currently 8 errors in compile)

2026-10-13 12:23:52 +11:00

register_file.sv

Added external register inspection code

2026-10-15 14:23:38 +11:00

rom.sv

Added 4 digit 7seg display module (confirmed working for now),

2026-10-13 16:32:15 +11:00

seven_seg_4digit.sv

Added 4 digit 7seg display module (confirmed working for now),

2026-10-13 16:32:15 +11:00

seven_seg.sv

Added header guards to prevent errors from double-inclusions

2026-09-13 23:09:08 +10:00

shifter.sv

Added Q5 comments and sumbission

2026-09-16 12:54:18 +10:00

shifter.sv.bak

Updated shifter (Q5) to use proper 2**width approach and corrected the logic such that C is width bits wide, and b is 2**width (as defined in Q5 B)

2026-09-15 19:43:28 +10:00

sign_extender.sv

Rewrote ternary operator to be less confusing

2026-10-15 14:04:36 +11:00