Merge branch 'main' of ssh://git.rileyk.au:19482/TroubleElectrical/FPGA_Uni

modules/assignment2.sv

@@ -12,7 +12,7 @@
 `include "seven_seg_4digit.sv"
 
 
-module assignment2 #(width=5, ramsz=9, romsz=10) (
+module assignment2 #(width=5, romsz=10) (
 	input logic [0:0] clk
 `ifdef QUARTUS_SYNTH
     ,
@@ -51,6 +51,10 @@ module assignment2 #(width=5, ramsz=9, romsz=10) (
 	logic [2**width-1:0] rd;
 	logic [0:0] rd_we;
 	logic [31:0] regs_out [32];
+
+    // ALU intermediates
+	logic [2**width-1:0] rd_alu;
+	logic [2**width-1:0] rt_alu;
 	
 	instruction_counter #(width) PC (clk, pc_we, pc_addr_write, pc_addr);
 	

modules/ram.sv

@@ -10,12 +10,12 @@ module ram #(addrwidth=9, datawidth=5)(
 );
 
     // TODO: Make this byte-sized, NOT word-sized!
-    logic [2**datawidth-1:0] mem[(2**(addrwidth+$clog2(datawidth)-3))-1:0];
+    logic [2**datawidth-1:0] mem[0:255];
 
     // NOTE: Possible issue with assignments still pending by end of initial block
     initial begin
-        for (integer ADDR = 0; ADDR < 2**(addrwidth+$clog2(datawidth)-3); ++ADDR) begin
-            mem[ADDR] <= 8'b0;
+        for (integer ADDR = 0; ADDR < 256); ADDR = ADDR + 1) begin
+            mem[ADDR] <= 32'b0;
         end
     end