Updated Assignment2 with better register file module insantiation

modules/assignment2.sv

@@ -74,17 +74,14 @@ module assignment2 #(width=5, ramsz=9, romsz=10) (
 		en_mul, 
 		en_alu
 	);
-<<<<<<< HEAD
-    
-	register_file #(width, 5) REGS (clk
-		rd_we, instruction[15:11],
-=======
 
-	register_file #(width, 5) REGS (clk,
-		rd_we, (F) ? instruction[15:11] : instruction[20:16],
->>>>>>> 1c93c082ae8b87f3d11223016ddd3c10fe1d845d
-		rs, instruction[25:21],
-		rt, instruction[20:16]
+
+	register_file #(width, 5) REGS (
+		clk, rd_we, 
+		(F) ? instruction[15:11] : instruction[20:16], rs,
+		instruction[25:21], rt, 
+		instruction[20:16], rd,
+		regs_out
    );
     // Always use sign-extension
     logic [2**width-1:0] rt_imm;
@@ -100,12 +97,12 @@ module assignment2 #(width=5, ramsz=9, romsz=10) (
 
 	assign rd_we = M;
 	assign pc_we = B1 & flags[2];
-	assign pc_addr_write <= (rt_imm << 2) + pc_addr;
+	assign pc_addr_write = (rt_imm << 2) + pc_addr;
 
 
 
 	// Temporary Test output
-	assign PC_Reg_Display = 16'hC342;
+	// assign PC_Reg_Display = 16'hC342;
 
    assign PC_Reg_Display = (HID_Hi_Low) ? regs_out[HID_Register][31:16] : regs_out[HID_Register][15:0];