Added 4 digit 7seg display module (confirmed working for now),

Added Inputs for displaying registers / Program Counter high and low bits,
Assigned pins for Display digits, inputs (Labeled HID) and the clk button

modules/assignment2.sv

@@ -9,54 +9,88 @@
 `include "instruction_module_classifier.sv"
 `include "alu.sv"
 `include "shifter.sv"
+`include "seven_seg_4digit.sv"
 
 
-
-module assignment2 #(width=5, ramsz=9, romsz=10) (input logic [0:0] clk);
-    logic [romsz-1:0] pc_addr;
-    logic [romsz-1:0] pc_addr_write;
-    logic [0:0] pc_we;
-    logic [2**width-1:0] instruction;
-
-    logic[0:0] R;
-    logic[0:0] B1;
-    logic[0:0] J;
-    logic[0:0] B2;
-    logic[0:0] I;
-    logic[0:0] F;
-    logic[0:0] M;
-
-    logic [0:0] en_shifter;
-    logic [0:0] en_jmp;
-    logic [0:0] en_mul;
-    logic [0:0] en_alu;
-
-    logic [1:0] flags;
-    logic [2**width-1:0] rs;
-    logic [2**width-1:0] rt;
-    logic [2**width-1:0] rd;
-    logic [0:0] rd_we;
-
-    instruction_counter #(width) PC (clk, pc_we, pc_addr_write, pc_addr);
-    rom #(romsz, 2**width) ROM (pc_addr, instruction);
-    instruction_classifier INSTRUCTION_CLASSIFIER(instruction[31:26], R, B1, J, B2, I, F, M);
-    instruction_module_classifier INSTRUCTION_MODULE_CLASSIFIER(instruction[5:3], en_shifter, en_jmp, en_mul, en_alu);
+module assignment2 #(width=5, ramsz=9, romsz=10) (
+	input logic [0:0] clk,
+	input logic [4:0] HID_Register,
+	input logic [0:0] HID_PC,
+	input logic [0:0] HID_Hi_Low,
+	
+	output logic[7:0] out_seg_0,
+	output logic[7:0] out_seg_1,
+	output logic[7:0] out_seg_2,
+	output logic[7:0] out_seg_3
+	);
+	// Intermediate for displaying high / low of PC or Register
+	logic[15:0] PC_Reg_Display;
+	
+	// Program / Instruction Counter Intermediates
+	logic [romsz-1:0] pc_addr;
+	logic [romsz-1:0] pc_addr_write;
+	logic [0:0] pc_we;
+	logic [2**width-1:0] instruction;
+	
+	// Instruction Classifier Intermediates
+	logic[0:0] R;
+	logic[0:0] B1;
+	logic[0:0] J;
+	logic[0:0] B2;
+	logic[0:0] I;
+	logic[0:0] F;
+	logic[0:0] M;
+	
+	// Instruction Module Classifier intermediates	
+	logic [0:0] en_shifter;
+	logic [0:0] en_jmp;
+	logic [0:0] en_mul;
+	logic [0:0] en_alu;
+	
+	// Register File intermediates
+	logic [1:0] flags;
+	logic [2**width-1:0] rs;
+	logic [2**width-1:0] rt;
+	logic [2**width-1:0] rd;
+	logic [0:0] rd_we;
+	
+	instruction_counter #(width) PC (clk, pc_we, pc_addr_write, pc_addr);
+	
+	rom #(romsz, 2**width) ROM (pc_addr, instruction);
+	
+	instruction_classifier INSTRUCTION_CLASSIFIER(instruction[31:26], R, B1, J, B2, I, F, M);
+	
+	instruction_module_classifier INSTRUCTION_MODULE_CLASSIFIER(instruction[5:3], 
+		en_shifter, 
+		en_jmp, 
+		en_mul, 
+		en_alu
+	);
     
-    register_file #(width, 5) REGS (clk,
-        rd_we, instruction[15:11],
-        rs, instruction[25:21],
-        rt, instruction[20:16]
-    );
+	register_file #(width, 5) REGS (clk,
+		rd_we, instruction[15:11],
+		rs, instruction[25:21],
+		rt, instruction[20:16]
+   );
 
-    logic [2**width-1:0] rd_alu;
-    alu #(width) ALU (instruction[3:0], rs, rt, rd_alu, flags[1:0]);
+	logic [2**width-1:0] rd_alu;
+	alu #(width) ALU (instruction[3:0], rs, rt, rd_alu, flags[1:0]);
 
-    logic [2**width-1:0] rd_shifter;
-    shifter #(width) SHIFTER (instruction[2:0], rt, rs[4:0], instruction[10:6], rd_shifter);
+	logic [2**width-1:0] rd_shifter;
+	shifter #(width) SHIFTER (instruction[2:0], rt, rs[4:0], instruction[10:6], rd_shifter);
     
-   assign rd = en_alu
-          ? rd_alu
-          : (en_shifter ? rd_shifter : {2**width{1'b0}});
+	assign rd = en_alu ? rd_alu : (en_shifter ? rd_shifter : {2**width{1'b0}});
+	
+	// Temporary Test output
+	assign PC_Reg_Display = 16'hC342;
+	
+	seven_seg_4digit display (
+		.num(PC_Reg_Display),
+		.segments0(out_seg_0),
+		.segments1(out_seg_1),
+		.segments2(out_seg_2),
+		.segments3(out_seg_3)
+	);
 
 endmodule
 `endif

modules/rom.sv

@@ -21,3 +21,4 @@ module rom #(parameter m=7,p=4) (
 endmodule // end rom module
 
 `endif
+

modules/seven_seg_4digit.sv

@@ -0,0 +1,44 @@
+`ifndef SEVEN_SEG_4_H_SV
+`define SEVEN_SEG_4_H_SV
+
+`include "seven_seg.sv"
+module seven_seg_4digit (
+    input  logic [15:0] num,
+    output logic [7:0]  segments0,
+    output logic [7:0]  segments1,
+    output logic [7:0]  segments2,
+    output logic [7:0]  segments3
+);
+
+    // Rightmost digit
+    seven_seg digit0 (
+        .num(num[3:0]),
+        .rbi_inv(1'b0),
+        .segments(segments0)
+    );
+
+    // Second digit from right
+    seven_seg digit1 (
+        .num(num[7:4]),
+        .rbi_inv(1'b0),
+        .segments(segments1)
+    );
+
+    // Third digit from right
+    seven_seg digit2 (
+        .num(num[11:8]),
+        .rbi_inv(1'b0),
+        .segments(segments2)
+    );
+
+    // Leftmost digit
+    seven_seg digit3 (
+        .num(num[15:12]),
+        .rbi_inv(1'b0),
+        .segments(segments3)
+    );
+
+endmodule
+
+`endif
+