Updated reg file and assignment for compilation

modules/assignment2.sv

@@ -57,6 +57,7 @@ module assignment2 #(width=5, ramsz=9, romsz=10) (
 	logic [2**width-1:0] rt;
 	logic [2**width-1:0] rd;
 	logic [0:0] rd_we;
+	logic [31:0] regs_out [32];
 	
 	instruction_counter #(width) PC (clk, pc_we, pc_addr_write, pc_addr);
 	
@@ -71,11 +72,10 @@ module assignment2 #(width=5, ramsz=9, romsz=10) (
 		en_alu
 	);
     
-	register_file #(width, 5) REGS (clk,
+	register_file #(width, 5) REGS (clk
 		rd_we, instruction[15:11],
 		rs, instruction[25:21],
-		rt, instruction[20:16],
-        regs_out 
+		rt, instruction[20:16]
    );
     // Always use sign-extension
     logic [2**width-1:0] rt_imm;
@@ -101,7 +101,7 @@ module assignment2 #(width=5, ramsz=9, romsz=10) (
 	// Temporary Test output
 	assign PC_Reg_Display = 16'hC342;
 
-    assign PC_Reg_Display = (HID_Hi_Low) ? regs_out[HID_Register][31:16] : regs_out[HID_Register][15:0];
+   assign PC_Reg_Display = (HID_Hi_Low) ? regs_out[HID_Register][31:16] : regs_out[HID_Register][15:0];
 	
 	seven_seg_4digit display (
 		.num(PC_Reg_Display),

modules/register_file.sv

@@ -5,7 +5,7 @@ module register_file #(parameter width=5, parameter nregs=5)(
     input logic [0:0] clk, input logic[0:0] we,
     input logic [nregs-1:0] WA, input logic [2**width-1:0] WD,
     input logic [nregs-1:0] RA1, output logic [2**width-1:0] RD1,
-    input logic [nregs-1:0] RA2, output logic [2**width-1:0] RD2
+    input logic [nregs-1:0] RA2, output logic [2**width-1:0] RD2,
     output logic [2**width-1:0] regs_out [2**nregs]
 );
     localparam BW = 2**width;