Made ROM binary file configurable via a parameter. Updated assignment2 and assignment3 to reflect this. Added bit slicing in assignment2 for ram/rom addresses.

modules/assignment2.sv

@@ -58,10 +58,15 @@ module assignment2 #(width=5, ramsz=9, romsz=10) (
 	
 	instruction_counter #(width) PC (clk, rst, pc_we, pc_addr_write, pc_addr);
 	
-	rom #(romsz, width) ROM (pc_addr, instruction);
+	`ifdef QUARTUS_SYNTH
+		rom #("../../asm/bin/ELEC4720-2026s2-Ass-02-Demo.hex", romsz, width) ROM (pc_addr[romsz-1:0], instruction);
+	`else
+		rom #("./asm/bin/ELEC4720-2026s2-Ass-02-Demo.hex", romsz, width) ROM (pc_addr[romsz-1:0], instruction);
+	`endif
+
 
 	logic [2**width-1:0] rd_mem;
-	ram #(ramsz, width) RAM (clk, rst, rd_alu, M2W, rt, rd_mem);
+	ram #(ramsz, width) RAM (clk, rst, rd_alu[ramsz-1:0], M2W, rt, rd_mem);
 	
 	control_unit CONTROL_UNIT (instruction[31:26], instruction[5:0],
 		M2R, M2W, B, ALU_FN, ALU_SRC, RDST, RW

modules/assignment3.sv

@@ -42,7 +42,7 @@ module assignment3 #(width=5, romsz=9, ramsz=10)(
 	logic [2**width-1:0] rom_rd;
 	logic [2**width-1:0] rom_addr;
 	logic [2**width-1:0] instruction, instruction_1;
-	rom #(romsz, width) ROM (rom_addr[romsz-1:0], rom_rd);
+	rom #("./asm/bin/ELEC4720-2026s2-Ass-03-NoHazardsDemo.hex", romsz, width) ROM (rom_addr[romsz-1:0], rom_rd);
 	gatereg #(width, 1) gate_pc_addr(clk, rst, 1'b1, pc_addr, rom_addr);
 	gatereg #(width, 1) gate_instruction(clk, rst, 1'b1, rom_rd, instruction);
 	gatereg #(width, 1) gate_instruction_1(clk, rst, 1'b1, instruction, instruction_1);
@@ -90,10 +90,10 @@ module assignment3 #(width=5, romsz=9, ramsz=10)(
 
 	logic [2**width-1:0] alu_out, alu_out_1, alu_out_2;
 	logic [3:0] alu_flags, alu_flags_1;
-	alu #(width) ALU (ALU_FN, regf_rs_1, (ALU_SRC) ? rt_imm : regf_rt_1, alu_out, alu_flags);
+	alu #(width) ALU (ALU_FN, regf_rs_1, (ALU_SRC) ? rt_imm : regf_rt_1, alu_out, alu_flags[2:0]);
 	gatereg #(width, 1) gate_alu_out (clk, rst, 1'b1, alu_out, alu_out_1);
 	gatereg #(width, 1) gate_alu_out_1 (clk, rst, 1'b1, alu_out_1, alu_out_2);
-	gatereg #(width, 1) gate_alu_flags (clk, rst, 1'b1, alu_flags, alu_flags_1);
+	gatereg #(2, 1) gate_alu_flags (clk, rst, 1'b1, alu_flags, alu_flags_1);
 	assign rd_alu = alu_out_2;
 
 	logic [2**width-1:0] new_pc_addr, new_pc_addr_1;
@@ -104,7 +104,7 @@ module assignment3 #(width=5, romsz=9, ramsz=10)(
 	assign pc_addr_write = new_pc_addr_1;
 	assign pc_we = B & alu_flags_1[2];
 	logic [2**width-1:0] mem_out, mem_out_1;
-	ram #(ramsz, width) RAM (clk, rst, alu_out_1, MEM_WE, regf_rt_2, mem_out);
+	ram #(ramsz, width) RAM (clk, rst, alu_out_1[ramsz-1:0], MEM_WE, regf_rt_2, mem_out);
 	gatereg #(width, 1) gate_mem_out (clk, rst, 1'b1, mem_out, mem_out_1);
 	assign rd_mem = mem_out_1;
 endmodule

modules/rom.sv

@@ -1,7 +1,7 @@
 `ifndef ROM_H
 `define ROM_H
 
-module rom #(parameter m=7,p=4) (
+module rom #(parameter string binary_path, parameter m=7,p=4) (
         input logic [m-1:0] Ad,
         output logic [2**p-1:0] Dout
     );
@@ -12,11 +12,7 @@ module rom #(parameter m=7,p=4) (
     //Load the program in memory
     // The machine code stored in text file program.dat written in Hex format
     initial begin
-        `ifdef QUARTUS_SYNTH
-            $readmemh("../../asm/bin/ELEC4720-2026s2-Ass-02-Demo.hex", mem, 0, 2**m-1); //$readmemb for binary
-        `else
-            $readmemh("./asm/bin/ELEC4720-2026s2-Ass-02-Demo.hex", mem, 0, 2**m-1); //$readmemb for binary
-        `endif
+        $readmemh(binary_path, mem, 0, 2**m-1); //$readmemb for binary
     end
 endmodule // end rom module