Added Hazard Unit file (tested compiling correctly) labelled variables inside off of the Assignment 3 Questions PDF Figure 2.

Also have a placeholder MUX to place before the ALU for adding hazard unit functionality

ModelSim/Assignment_1_Q2.cr.mti

@@ -1,11 +1,4 @@
-/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/lu.sv {1 {vlog -work work -sv -stats=none /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/lu.sv
+/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/lu_tb.sv {1 {vlog -work work -sv -stats=none /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/lu_tb.sv
-Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
--- Compiling module lu
-
-Top level modules:
-	lu
-
-} {} {}} /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/lu_tb.sv {1 {vlog -work work -sv -stats=none /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/lu_tb.sv
 Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
 -- Compiling module lu
 -- Compiling module lu_tb

ModelSim/Assignment_2.cr.mti

@@ -0,0 +1,234 @@
+/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/shifter.sv {1 {vlog -work work -sv -stats=none /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/shifter.sv
+Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
+-- Compiling module shifter
+
+Top level modules:
+	shifter
+
+} {} {}} /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/rom.sv {1 {vlog -work work -sv -stats=none /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/rom.sv
+Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
+-- Compiling module rom
+
+Top level modules:
+	rom
+
+} {} {}} /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/instruction_classifier.sv {1 {vlog -work work -sv -stats=none /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/instruction_classifier.sv
+Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
+-- Compiling module instruction_classifier
+
+Top level modules:
+	instruction_classifier
+
+} {} {}} /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/seven_seg.sv {1 {vlog -work work -sv -stats=none /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/seven_seg.sv
+Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
+-- Compiling module seven_seg
+
+Top level modules:
+	seven_seg
+
+} {} {}} /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/ram.sv {1 {vlog -work work -sv -stats=none /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/ram.sv
+Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
+-- Compiling module ram
+
+Top level modules:
+	ram
+
+} {} {}} /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/control_unit.sv {1 {vlog -work work -sv -stats=none /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/control_unit.sv
+Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
+-- Compiling module instruction_classifier
+-- Compiling module control_unit
+
+Top level modules:
+	control_unit
+
+} {} {}} /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/mips.sv {1 {vlog -work work -sv -stats=none /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/mips.sv
+Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
+-- Compiling module rom
+-- Compiling module ram
+-- Compiling module register_file
+-- Compiling module instruction_counter
+-- Compiling module instruction_classifier
+-- Compiling module control_unit
+-- Compiling module asu
+-- Compiling module lu
+-- Compiling module alu
+-- Compiling module shifter
+-- Compiling module sign_extender
+-- Compiling module seven_seg
+-- Compiling module seven_seg_4digit
+-- Compiling module assignment2
+-- Compiling module mips_tb
+
+Top level modules:
+	shifter
+	seven_seg_4digit
+	mips_tb
+
+} {} {}} /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/asu.sv {1 {vlog -work work -sv -stats=none /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/asu.sv
+Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
+-- Compiling module asu
+
+Top level modules:
+	asu
+
+} {} {}} /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/lu.sv {1 {vlog -work work -sv -stats=none /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/lu.sv
+Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
+-- Compiling module lu
+
+Top level modules:
+	lu
+
+} {} {}} /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/shifter_tb.sv {1 {vlog -work work -sv -stats=none /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/shifter_tb.sv
+Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
+-- Compiling module shifter
+-- Compiling module shifter_tb
+
+Top level modules:
+	shifter_tb
+
+} {} {}} /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/assignment2.sv {1 {vlog -work work -sv -stats=none /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/assignment2.sv
+Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
+-- Compiling module rom
+-- Compiling module ram
+-- Compiling module register_file
+-- Compiling module instruction_counter
+-- Compiling module instruction_classifier
+-- Compiling module control_unit
+-- Compiling module asu
+-- Compiling module lu
+-- Compiling module alu
+-- Compiling module shifter
+-- Compiling module sign_extender
+-- Compiling module seven_seg
+-- Compiling module seven_seg_4digit
+-- Compiling module assignment2
+
+Top level modules:
+	shifter
+	seven_seg_4digit
+	assignment2
+
+} {} {}} /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/seven_seg_tb.sv {1 {vlog -work work -sv -stats=none /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/seven_seg_tb.sv
+Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
+-- Compiling module seven_seg
+-- Compiling module seven_seg_tb
+
+Top level modules:
+	seven_seg_tb
+
+} {} {}} /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/asu_tb.sv {1 {vlog -work work -sv -stats=none /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/asu_tb.sv
+Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
+-- Compiling module asu
+-- Compiling module asu_tb
+
+Top level modules:
+	asu_tb
+
+} {} {}} /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/lu_tb.sv {1 {vlog -work work -sv -stats=none /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/lu_tb.sv
+Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
+-- Compiling module lu
+-- Compiling module lu_tb
+
+Top level modules:
+	lu_tb
+
+} {} {}} /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/alu_tb.sv {1 {vlog -work work -sv -stats=none /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/alu_tb.sv
+Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
+-- Compiling module asu
+-- Compiling module lu
+-- Compiling module alu
+-- Compiling module alu_tb
+
+Top level modules:
+	alu_tb
+
+} {} {}} /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/sign_extender.sv {1 {vlog -work work -sv -stats=none /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/sign_extender.sv
+Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
+-- Compiling module sign_extender
+
+Top level modules:
+	sign_extender
+
+} {} {}} /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/gatereg.sv {1 {vlog -work work -sv -stats=none /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/gatereg.sv
+Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
+-- Compiling module gatereg
+
+Top level modules:
+	gatereg
+
+} {} {}} /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/hazard_unit.sv {1 {vlog -work work -sv -stats=none /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/hazard_unit.sv
+Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
+-- Compiling module hazard_unit
+
+Top level modules:
+	hazard_unit
+
+} {} {}} /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/instruction_counter.sv {1 {vlog -work work -sv -stats=none /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/instruction_counter.sv
+Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
+-- Compiling module instruction_counter
+
+Top level modules:
+	instruction_counter
+
+} {} {}} /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/alu.sv {1 {vlog -work work -sv -stats=none /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/alu.sv
+Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
+-- Compiling module asu
+-- Compiling module lu
+-- Compiling module alu
+
+Top level modules:
+	alu
+
+} {} {}} /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/ByteIM.sv {1 {vlog -work work -sv -stats=none /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/ByteIM.sv
+Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
+-- Compiling module rom
+-- Compiling module ByteIM
+
+Top level modules:
+	rom
+	ByteIM
+
+} {} {}} /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/instruction_classifier_tb.sv {1 {vlog -work work -sv -stats=none /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/instruction_classifier_tb.sv
+Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
+-- Compiling module instruction_classifier
+-- Compiling module instruction_classifier_tb
+
+Top level modules:
+	instruction_classifier_tb
+
+} {} {}} /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/seven_seg_4digit.sv {1 {vlog -work work -sv -stats=none /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/seven_seg_4digit.sv
+Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
+-- Compiling module seven_seg
+-- Compiling module seven_seg_4digit
+
+Top level modules:
+	seven_seg_4digit
+
+} {} {}} /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/register_file.sv {1 {vlog -work work -sv -stats=none /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/register_file.sv
+Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
+-- Compiling module register_file
+
+Top level modules:
+	register_file
+
+} {} {}} /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/assignment3.sv {1 {vlog -work work -sv -stats=none /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/assignment3.sv
+Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
+-- Compiling module rom
+-- Compiling module ram
+-- Compiling module register_file
+-- Compiling module instruction_counter
+-- Compiling module instruction_classifier
+-- Compiling module control_unit
+-- Compiling module asu
+-- Compiling module lu
+-- Compiling module alu
+-- Compiling module shifter
+-- Compiling module sign_extender
+-- Compiling module gatereg
+-- Compiling module assignment3
+
+Top level modules:
+	shifter
+	assignment3
+
+} {} {}}

ModelSim/Assignment_2.mpf

@@ -0,0 +1,512 @@
+; Copyright 1991-2009 Mentor Graphics Corporation
+;
+; All Rights Reserved.
+;
+; THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH IS THE PROPERTY OF 
+; MENTOR GRAPHICS CORPORATION OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS.
+;   
+
+[Library]
+std = $MODEL_TECH/../std
+ieee = $MODEL_TECH/../ieee
+verilog = $MODEL_TECH/../verilog
+vital2000 = $MODEL_TECH/../vital2000
+std_developerskit = $MODEL_TECH/../std_developerskit
+synopsys = $MODEL_TECH/../synopsys
+modelsim_lib = $MODEL_TECH/../modelsim_lib
+sv_std = $MODEL_TECH/../sv_std
+
+; Altera Primitive libraries
+;
+; VHDL Section
+;
+altera_mf = $MODEL_TECH/../altera/vhdl/altera_mf
+altera = $MODEL_TECH/../altera/vhdl/altera
+altera_lnsim = $MODEL_TECH/../altera/vhdl/altera_lnsim
+lpm = $MODEL_TECH/../altera/vhdl/220model
+220model = $MODEL_TECH/../altera/vhdl/220model
+maxii = $MODEL_TECH/../altera/vhdl/maxii
+maxv = $MODEL_TECH/../altera/vhdl/maxv
+fiftyfivenm = $MODEL_TECH/../altera/vhdl/fiftyfivenm
+sgate = $MODEL_TECH/../altera/vhdl/sgate
+arriaii = $MODEL_TECH/../altera/vhdl/arriaii
+arriaii_hssi = $MODEL_TECH/../altera/vhdl/arriaii_hssi
+arriaii_pcie_hip = $MODEL_TECH/../altera/vhdl/arriaii_pcie_hip
+arriaiigz = $MODEL_TECH/../altera/vhdl/arriaiigz
+arriaiigz_hssi = $MODEL_TECH/../altera/vhdl/arriaiigz_hssi
+arriaiigz_pcie_hip = $MODEL_TECH/../altera/vhdl/arriaiigz_pcie_hip
+stratixiv = $MODEL_TECH/../altera/vhdl/stratixiv
+stratixiv_hssi = $MODEL_TECH/../altera/vhdl/stratixiv_hssi
+stratixiv_pcie_hip = $MODEL_TECH/../altera/vhdl/stratixiv_pcie_hip
+cycloneiv = $MODEL_TECH/../altera/vhdl/cycloneiv
+cycloneiv_hssi = $MODEL_TECH/../altera/vhdl/cycloneiv_hssi
+cycloneiv_pcie_hip = $MODEL_TECH/../altera/vhdl/cycloneiv_pcie_hip
+cycloneive = $MODEL_TECH/../altera/vhdl/cycloneive
+stratixv = $MODEL_TECH/../altera/vhdl/stratixv
+stratixv_hssi = $MODEL_TECH/../altera/vhdl/stratixv_hssi
+stratixv_pcie_hip = $MODEL_TECH/../altera/vhdl/stratixv_pcie_hip
+arriavgz = $MODEL_TECH/../altera/vhdl/arriavgz
+arriavgz_hssi = $MODEL_TECH/../altera/vhdl/arriavgz_hssi
+arriavgz_pcie_hip = $MODEL_TECH/../altera/vhdl/arriavgz_pcie_hip
+arriav = $MODEL_TECH/../altera/vhdl/arriav
+cyclonev = $MODEL_TECH/../altera/vhdl/cyclonev
+twentynm = $MODEL_TECH/../altera/vhdl/twentynm
+twentynm_hssi = $MODEL_TECH/../altera/vhdl/twentynm_hssi
+twentynm_hip = $MODEL_TECH/../altera/vhdl/twentynm_hip
+cyclone10lp = $MODEL_TECH/../altera/vhdl/cyclone10lp
+;
+; Verilog Section
+;
+altera_mf_ver = $MODEL_TECH/../altera/verilog/altera_mf
+altera_ver = $MODEL_TECH/../altera/verilog/altera
+altera_lnsim_ver = $MODEL_TECH/../altera/verilog/altera_lnsim
+lpm_ver = $MODEL_TECH/../altera/verilog/220model
+220model_ver = $MODEL_TECH/../altera/verilog/220model
+maxii_ver = $MODEL_TECH/../altera/verilog/maxii
+maxv_ver = $MODEL_TECH/../altera/verilog/maxv
+fiftyfivenm_ver = $MODEL_TECH/../altera/verilog/fiftyfivenm
+sgate_ver = $MODEL_TECH/../altera/verilog/sgate
+arriaii_ver = $MODEL_TECH/../altera/verilog/arriaii
+arriaii_hssi_ver = $MODEL_TECH/../altera/verilog/arriaii_hssi
+arriaii_pcie_hip_ver = $MODEL_TECH/../altera/verilog/arriaii_pcie_hip
+arriaiigz_ver = $MODEL_TECH/../altera/verilog/arriaiigz
+arriaiigz_hssi_ver = $MODEL_TECH/../altera/verilog/arriaiigz_hssi
+arriaiigz_pcie_hip_ver = $MODEL_TECH/../altera/verilog/arriaiigz_pcie_hip
+stratixiv_ver = $MODEL_TECH/../altera/verilog/stratixiv
+stratixiv_hssi_ver = $MODEL_TECH/../altera/verilog/stratixiv_hssi
+stratixiv_pcie_hip_ver = $MODEL_TECH/../altera/verilog/stratixiv_pcie_hip
+stratixv_ver = $MODEL_TECH/../altera/verilog/stratixv
+stratixv_hssi_ver = $MODEL_TECH/../altera/verilog/stratixv_hssi
+stratixv_pcie_hip_ver = $MODEL_TECH/../altera/verilog/stratixv_pcie_hip
+arriavgz_ver = $MODEL_TECH/../altera/verilog/arriavgz
+arriavgz_hssi_ver = $MODEL_TECH/../altera/verilog/arriavgz_hssi
+arriavgz_pcie_hip_ver = $MODEL_TECH/../altera/verilog/arriavgz_pcie_hip
+arriav_ver = $MODEL_TECH/../altera/verilog/arriav
+arriav_hssi_ver = $MODEL_TECH/../altera/verilog/arriav_hssi
+arriav_pcie_hip_ver = $MODEL_TECH/../altera/verilog/arriav_pcie_hip
+cyclonev_ver = $MODEL_TECH/../altera/verilog/cyclonev
+cyclonev_hssi_ver = $MODEL_TECH/../altera/verilog/cyclonev_hssi
+cyclonev_pcie_hip_ver = $MODEL_TECH/../altera/verilog/cyclonev_pcie_hip
+cycloneiv_ver = $MODEL_TECH/../altera/verilog/cycloneiv
+cycloneiv_hssi_ver = $MODEL_TECH/../altera/verilog/cycloneiv_hssi
+cycloneiv_pcie_hip_ver = $MODEL_TECH/../altera/verilog/cycloneiv_pcie_hip
+cycloneive_ver = $MODEL_TECH/../altera/verilog/cycloneive
+twentynm_ver = $MODEL_TECH/../altera/verilog/twentynm
+twentynm_hssi_ver = $MODEL_TECH/../altera/verilog/twentynm_hssi
+twentynm_hip_ver = $MODEL_TECH/../altera/verilog/twentynm_hip
+cyclone10lp_ver = $MODEL_TECH/../altera/verilog/cyclone10lp
+
+work = work
+[vcom]
+; VHDL93 variable selects language version as the default. 
+; Default is VHDL-2002.
+; Value of 0 or 1987 for VHDL-1987.
+; Value of 1 or 1993 for VHDL-1993.
+; Default or value of 2 or 2002 for VHDL-2002.
+; Default or value of 3 or 2008 for VHDL-2008.
+VHDL93 = 2002
+
+; Show source line containing error. Default is off.
+; Show_source = 1
+
+; Turn off unbound-component warnings. Default is on.
+; Show_Warning1 = 0
+
+; Turn off process-without-a-wait-statement warnings. Default is on.
+; Show_Warning2 = 0
+
+; Turn off null-range warnings. Default is on.
+; Show_Warning3 = 0
+
+; Turn off no-space-in-time-literal warnings. Default is on.
+; Show_Warning4 = 0
+
+; Turn off multiple-drivers-on-unresolved-signal warnings. Default is on.
+; Show_Warning5 = 0
+
+; Turn off optimization for IEEE std_logic_1164 package. Default is on.
+; Optimize_1164 = 0
+
+; Turn on resolving of ambiguous function overloading in favor of the
+; "explicit" function declaration (not the one automatically created by
+; the compiler for each type declaration). Default is off.
+; The .ini file has Explicit enabled so that std_logic_signed/unsigned
+; will match the behavior of synthesis tools.
+Explicit = 1
+
+; Turn off acceleration of the VITAL packages. Default is to accelerate.
+; NoVital = 1
+
+; Turn off VITAL compliance checking. Default is checking on.
+; NoVitalCheck = 1
+
+; Ignore VITAL compliance checking errors. Default is to not ignore.
+; IgnoreVitalErrors = 1
+
+; Turn off VITAL compliance checking warnings. Default is to show warnings.
+; Show_VitalChecksWarnings = 0
+
+; Keep silent about case statement static warnings.
+; Default is to give a warning.
+; NoCaseStaticError = 1
+
+; Keep silent about warnings caused by aggregates that are not locally static.
+; Default is to give a warning.
+; NoOthersStaticError = 1
+
+; Turn off inclusion of debugging info within design units.
+; Default is to include debugging info.
+; NoDebug = 1
+
+; Turn off "Loading..." messages. Default is messages on.
+; Quiet = 1
+
+; Turn on some limited synthesis rule compliance checking. Checks only:
+;    -- signals used (read) by a process must be in the sensitivity list
+; CheckSynthesis = 1
+
+; Activate optimizations on expressions that do not involve signals,
+; waits, or function/procedure/task invocations. Default is off.
+; ScalarOpts = 1
+
+; Require the user to specify a configuration for all bindings,
+; and do not generate a compile time default binding for the
+; component. This will result in an elaboration error of
+; 'component not bound' if the user fails to do so. Avoids the rare
+; issue of a false dependency upon the unused default binding.
+; RequireConfigForAllDefaultBinding = 1
+
+; Inhibit range checking on subscripts of arrays. Range checking on
+; scalars defined with subtypes is inhibited by default.
+; NoIndexCheck = 1
+
+; Inhibit range checks on all (implicit and explicit) assignments to
+; scalar objects defined with subtypes.
+; NoRangeCheck = 1
+
+[vlog]
+
+; Turn off inclusion of debugging info within design units.
+; Default is to include debugging info.
+; NoDebug = 1
+
+; Turn off "loading..." messages. Default is messages on.
+; Quiet = 1
+
+; Turn on Verilog hazard checking (order-dependent accessing of global vars).
+; Default is off.
+; Hazard = 1
+
+; Turn on converting regular Verilog identifiers to uppercase. Allows case
+; insensitivity for module names. Default is no conversion.
+; UpCase = 1
+
+; Turn on incremental compilation of modules. Default is off.
+; Incremental = 1
+
+; Turns on lint-style checking.
+; Show_Lint = 1
+
+[vsim]
+; Simulator resolution
+; Set to fs, ps, ns, us, ms, or sec with optional prefix of 1, 10, or 100.
+Resolution = ps
+
+; User time unit for run commands
+; Set to default, fs, ps, ns, us, ms, or sec. The default is to use the
+; unit specified for Resolution. For example, if Resolution is 100ps,
+; then UserTimeUnit defaults to ps.
+; Should generally be set to default.
+UserTimeUnit = default
+
+; Default run length
+RunLength = 1 us
+
+; Maximum iterations that can be run without advancing simulation time
+IterationLimit = 5000
+
+; Directive to license manager:
+; vhdl          Immediately reserve a VHDL license
+; vlog          Immediately reserve a Verilog license
+; plus          Immediately reserve a VHDL and Verilog license
+; nomgc         Do not look for Mentor Graphics Licenses
+; nomti         Do not look for Model Technology Licenses
+; noqueue       Do not wait in the license queue when a license isn't available
+; viewsim	Try for viewer license but accept simulator license(s) instead
+;		of queuing for viewer license
+; License = plus
+
+; Stop the simulator after a VHDL/Verilog assertion message
+; 0 = Note  1 = Warning  2 = Error  3 = Failure  4 = Fatal
+BreakOnAssertion = 3
+
+; Assertion Message Format
+; %S - Severity Level 
+; %R - Report Message
+; %T - Time of assertion
+; %D - Delta
+; %I - Instance or Region pathname (if available)
+; %% - print '%' character
+; AssertionFormat = "** %S: %R\n   Time: %T  Iteration: %D%I\n"
+
+; Assertion File - alternate file for storing VHDL/Verilog assertion messages
+; AssertFile = assert.log
+
+; Default radix for all windows and commands...
+; Set to symbolic, ascii, binary, octal, decimal, hex, unsigned
+DefaultRadix = symbolic
+
+; VSIM Startup command
+; Startup = do startup.do
+
+; File for saving command transcript
+TranscriptFile = transcript
+
+; File for saving command history
+; CommandHistory = cmdhist.log
+
+; Specify whether paths in simulator commands should be described
+; in VHDL or Verilog format.
+; For VHDL, PathSeparator = /
+; For Verilog, PathSeparator = .
+; Must not be the same character as DatasetSeparator.
+PathSeparator = /
+
+; Specify the dataset separator for fully rooted contexts.
+; The default is ':'. For example, sim:/top
+; Must not be the same character as PathSeparator.
+DatasetSeparator = :
+
+; Disable VHDL assertion messages
+; IgnoreNote = 1
+; IgnoreWarning = 1
+; IgnoreError = 1
+; IgnoreFailure = 1
+
+; Default force kind. May be freeze, drive, deposit, or default
+; or in other terms, fixed, wired, or charged.
+; A value of "default" will use the signal kind to determine the
+; force kind, drive for resolved signals, freeze for unresolved signals
+; DefaultForceKind = freeze
+
+; If zero, open files when elaborated; otherwise, open files on
+; first read or write.  Default is 0.
+; DelayFileOpen = 1
+
+; Control VHDL files opened for write.
+;   0 = Buffered, 1 = Unbuffered
+UnbufferedOutput = 0
+
+; Control the number of VHDL files open concurrently.
+; This number should always be less than the current ulimit
+; setting for max file descriptors.
+;   0 = unlimited
+ConcurrentFileLimit = 40
+
+; Control the number of hierarchical regions displayed as
+; part of a signal name shown in the Wave window.
+; A value of zero tells VSIM to display the full name.
+; The default is 0.
+; WaveSignalNameWidth = 0
+
+; Turn off warnings from the std_logic_arith, std_logic_unsigned
+; and std_logic_signed packages.
+; StdArithNoWarnings = 1
+
+; Turn off warnings from the IEEE numeric_std and numeric_bit packages.
+; NumericStdNoWarnings = 1
+
+; Control the format of the (VHDL) FOR generate statement label
+; for each iteration.  Do not quote it.
+; The format string here must contain the conversion codes %s and %d,
+; in that order, and no other conversion codes.  The %s represents
+; the generate_label; the %d represents the generate parameter value
+; at a particular generate iteration (this is the position number if
+; the generate parameter is of an enumeration type).  Embedded whitespace
+; is allowed (but discouraged); leading and trailing whitespace is ignored.
+; Application of the format must result in a unique scope name over all
+; such names in the design so that name lookup can function properly.
+; GenerateFormat = %s__%d
+
+; Specify whether checkpoint files should be compressed.
+; The default is 1 (compressed).
+; CheckpointCompressMode = 0
+
+; List of dynamically loaded objects for Verilog PLI applications
+; Veriuser = veriuser.sl
+
+; Specify default options for the restart command. Options can be one
+; or more of: -force -nobreakpoint -nolist -nolog -nowave
+; DefaultRestartOptions = -force
+
+; HP-UX 10.20 ONLY - Enable memory locking to speed up large designs
+; (> 500 megabyte memory footprint). Default is disabled.
+; Specify number of megabytes to lock.
+; LockedMemory = 1000
+
+; Turn on (1) or off (0) WLF file compression.
+; The default is 1 (compress WLF file).
+; WLFCompress = 0
+
+; Specify whether to save all design hierarchy (1) in the WLF file
+; or only regions containing logged signals (0).
+; The default is 0 (save only regions with logged signals).
+; WLFSaveAllRegions = 1
+
+; WLF file time limit.  Limit WLF file by time, as closely as possible,
+; to the specified amount of simulation time.  When the limit is exceeded
+; the earliest times get truncated from the file.
+; If both time and size limits are specified the most restrictive is used.
+; UserTimeUnits are used if time units are not specified.
+; The default is 0 (no limit).  Example: WLFTimeLimit = {100 ms}
+; WLFTimeLimit = 0
+
+; WLF file size limit.  Limit WLF file size, as closely as possible,
+; to the specified number of megabytes.  If both time and size limits
+; are specified then the most restrictive is used.
+; The default is 0 (no limit).
+; WLFSizeLimit = 1000
+
+; Specify whether or not a WLF file should be deleted when the
+; simulation ends.  A value of 1 will cause the WLF file to be deleted.
+; The default is 0 (do not delete WLF file when simulation ends).
+; WLFDeleteOnQuit = 1
+
+; Automatic SDF compilation
+; Disables automatic compilation of SDF files in flows that support it.
+; Default is on, uncomment to turn off.
+; NoAutoSDFCompile = 1
+
+[lmc]
+
+[msg_system]
+; Change a message severity or suppress a message.
+; The format is: <msg directive> = <msg number>[,<msg number>...]
+; Examples:
+;   note = 3009
+;   warning = 3033
+;   error = 3010,3016
+;   fatal = 3016,3033
+;   suppress = 3009,3016,3043
+; The command verror <msg number> can be used to get the complete
+; description of a message.
+
+; Control transcripting of elaboration/runtime messages.
+; The default is to have messages appear in the transcript and 
+; recorded in the wlf file (messages that are recorded in the
+; wlf file can be viewed in the MsgViewer).  The other settings
+; are to send messages only to the transcript or only to the 
+; wlf file.  The valid values are
+;    both  {default}
+;    tran  {transcript only}
+;    wlf   {wlf file only}
+; msgmode = both
+[Project]
+** Warning: ; Warning -- Do not edit the project properties directly.
+;            Property names are dynamic in nature and property
+;            values have special syntax.  Changing property data directly
+;            can result in a corrupt MPF file.  All project properties
+;            can be modified through project window dialogs.
+Project_Version = 6
+Project_DefaultLib = work
+Project_SortMethod = unused
+Project_Files_Count = 25
+Project_File_0 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/shifter.sv
+Project_File_P_0 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1790228042 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 19 dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_1 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/rom.sv
+Project_File_P_1 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 last_compile 1792112234 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 15 dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_2 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/instruction_classifier.sv
+Project_File_P_2 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1790228042 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 7 dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_3 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/seven_seg.sv
+Project_File_P_3 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1790228042 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 16 dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_4 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/ram.sv
+Project_File_P_4 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1792473740 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 13 dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_5 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/control_unit.sv
+Project_File_P_5 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1792112234 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 6 dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_6 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/mips.sv
+Project_File_P_6 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 folder {Top Level} last_compile 1792115823 cover_fsm 0 cover_branch 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 vlog_showsource 0 vlog_hazard 0 cover_optlevel 3 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 12 cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_7 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/asu.sv
+Project_File_P_7 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1790228118 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 3 dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_8 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/lu.sv
+Project_File_P_8 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1790228042 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 10 dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_9 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/shifter_tb.sv
+Project_File_P_9 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1789513270 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 20 dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_10 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/assignment2.sv
+Project_File_P_10 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1792119882 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 2 dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_11 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/seven_seg_tb.sv
+Project_File_P_11 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1788418794 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 18 dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_12 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/asu_tb.sv
+Project_File_P_12 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1789513270 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 4 dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_13 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/lu_tb.sv
+Project_File_P_13 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1788926090 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 11 dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_14 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/sign_extender.sv
+Project_File_P_14 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1792644107 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 vlog_showsource 0 vlog_hazard 0 cover_optlevel 3 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 21 cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_15 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/alu_tb.sv
+Project_File_P_15 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1789355084 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 1 dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_16 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/gatereg.sv
+Project_File_P_16 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 folder {Top Level} last_compile 1793848262 cover_fsm 0 cover_branch 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 23 dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_17 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/hazard_unit.sv
+Project_File_P_17 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1794101042 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 vlog_showsource 0 vlog_hazard 0 cover_optlevel 3 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 24 cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_18 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/instruction_counter.sv
+Project_File_P_18 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 folder {Top Level} last_compile 1792113810 cover_fsm 0 cover_branch 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 vlog_showsource 0 vlog_hazard 0 cover_optlevel 3 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 9 cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_19 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/alu.sv
+Project_File_P_19 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1792115823 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 vlog_showsource 0 vlog_hazard 0 cover_optlevel 3 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 0 cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_20 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/ByteIM.sv
+Project_File_P_20 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 last_compile 1793848949 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 5 dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_21 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/seven_seg_4digit.sv
+Project_File_P_21 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1792119097 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 vlog_showsource 0 vlog_hazard 0 cover_optlevel 3 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 17 cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_22 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/instruction_classifier_tb.sv
+Project_File_P_22 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1789355084 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 8 dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_23 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/register_file.sv
+Project_File_P_23 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1792112234 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 14 dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_24 = /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/assignment3.sv
+Project_File_P_24 = cover_toggle 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 folder {Top Level} last_compile 1793848882 cover_fsm 0 cover_branch 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 22 dont_compile 0 cover_expr 0 cover_stmt 0
+Project_Sim_Count = 0
+Project_Folder_Count = 0
+Echo_Compile_Output = 0
+Save_Compile_Report = 1
+Project_Opt_Count = 0
+ForceSoftPaths = 0
+ProjectStatusDelay = 5000
+VERILOG_DoubleClick = Edit
+VERILOG_CustomDoubleClick = 
+SYSTEMVERILOG_DoubleClick = Edit
+SYSTEMVERILOG_CustomDoubleClick = 
+VHDL_DoubleClick = Edit
+VHDL_CustomDoubleClick = 
+PSL_DoubleClick = Edit
+PSL_CustomDoubleClick = 
+TEXT_DoubleClick = Edit
+TEXT_CustomDoubleClick = 
+SYSTEMC_DoubleClick = Edit
+SYSTEMC_CustomDoubleClick = 
+TCL_DoubleClick = Edit
+TCL_CustomDoubleClick = 
+MACRO_DoubleClick = Edit
+MACRO_CustomDoubleClick = 
+VCD_DoubleClick = Edit
+VCD_CustomDoubleClick = 
+SDF_DoubleClick = Edit
+SDF_CustomDoubleClick = 
+XML_DoubleClick = Edit
+XML_CustomDoubleClick = 
+LOGFILE_DoubleClick = Edit
+LOGFILE_CustomDoubleClick = 
+UCDB_DoubleClick = Edit
+UCDB_CustomDoubleClick = 
+TDB_DoubleClick = Edit
+TDB_CustomDoubleClick = 
+UPF_DoubleClick = Edit
+UPF_CustomDoubleClick = 
+PCF_DoubleClick = Edit
+PCF_CustomDoubleClick = 
+PROJECT_DoubleClick = Edit
+PROJECT_CustomDoubleClick = 
+VRM_DoubleClick = Edit
+VRM_CustomDoubleClick = 
+DEBUGDATABASE_DoubleClick = Edit
+DEBUGDATABASE_CustomDoubleClick = 
+DEBUGARCHIVE_DoubleClick = Edit
+DEBUGARCHIVE_CustomDoubleClick = 
+Project_Major_Version = 2020
+Project_Minor_Version = 1

ModelSim/ByteIM.sv

@@ -0,0 +1,14 @@
+`include "rom.sv"
+
+module ByteIM #(parameter m=5,n=2) (
+    input logic [m-1:0] Ad,
+    output logic [(2**n)*8-1:0] Dout );
+
+    // 2**n byte wide words
+    // m bit wide byte address
+    // 2**m bytes of memory
+    // 2**(m-n) memory words
+    // 2**(n+3) bit wide words
+    // Reads the whole word that contains the addressed byte
+    ROM #(m-n,2**(n+3)) wordrom(Ad[m-1:n],Dout);
+endmodule

ModelSim/ByteIM.sv.bak

@@ -0,0 +1,14 @@
+`include "rom.sv"
+
+module ByteIM #(parameter m=5,n=2) (
+    input logic [m-1:0] Ad,
+    output logic [(2**n)*8-1:0] Dout );
+
+    // 2**n byte wide words
+    // m bit wide byte address
+    // 2**m bytes of memory
+    // 2**(m-n) memory words
+    // 2**(n+3) bit wide words
+    // Reads the whole word that contains the addressed byte
+    ROM #(m-n,2**(n+3)) wordrom(Ad[m-1:n],Dout)
+endmodule

ModelSim/alu.sv

@@ -6,32 +6,40 @@
 
 // flags[0:0] = Cout
 // flags[1:1] = Overflow
+// flags[2:2] = Zero
 module alu #(parameter width=2)(input logic [3:0] op,
     input logic [2**width-1:0] A, input logic [2**width-1:0] B,
-    output logic [2**width-1:0] OUT_1, output logic[1:0] flags);
+    output logic [2**width-1:0] OUT_1, output logic[2:0] flags
-
+    );
+    // intermediate logic for handling asu output
     logic [0:0] asu_op;
     logic [2**width-1:0] asu_out;
-    logic [1:0] asu_flags;
+    logic [2:0] asu_flags;
-    asu #(width) adder_unit(asu_op[op[1]], A, B, asu_out, asu_flags[0], asu_flags[1]);
+
+    assign asu_op = op[1];
+    logic [0:0] asu_cout_flag;
+    asu #(width) adder_unit(asu_op, A, B, asu_out, asu_flags[0], asu_cout_flag);
 
     logic [2**width-1:0] lu_out;
     lu #(width) logic_unit(op[1:0], A, B, lu_out);
 
+    assign asu_flags[1] = asu_cout_flag ^ asu_flags[0];
     always_comb begin
         case (op) 
-            4'b0000: begin OUT_1 = asu_out; flags = asu_flags; end
+            4'b0000: begin OUT_1 = asu_out; end
-            4'b0001: begin OUT_1 = asu_out; flags = asu_flags; end
+            4'b0001: begin OUT_1 = asu_out; end
-            4'b0010: begin OUT_1 = asu_out; flags = asu_flags; end
+            4'b0010: begin OUT_1 = asu_out; end
-            4'b0011: begin OUT_1 = asu_out; flags = asu_flags; end
+            4'b0011: begin OUT_1 = asu_out; end
-            4'b0100: begin OUT_1 = lu_out; flags = asu_flags; end
+            4'b0100: begin OUT_1 = lu_out; end
-            4'b0101: begin OUT_1 = lu_out; flags = asu_flags; end
+            4'b0101: begin OUT_1 = lu_out; end
-            4'b0110: begin OUT_1 = lu_out;  flags = asu_flags; end
+            4'b0110: begin OUT_1 = lu_out; end
-            4'b0111: begin OUT_1 = lu_out; flags = asu_flags; end
+            4'b0111: begin OUT_1 = lu_out; end
-            4'b1010: begin OUT_1 = (asu_out[2**width-1] ^ asu_flags[1]) & {{(width-1){1'b0}}, 1'b1}; flags = asu_flags; end
+            4'b1010: begin OUT_1 = (asu_out[2**width-1] ^ asu_flags[1]) & {{(width-1){1'b0}}, 1'b1}; end
-            4'b1011: begin OUT_1 = ~asu_flags[0] & {{(width-1){1'b0}}, 1'b1}; flags = asu_flags; end
+            4'b1011: begin OUT_1 = ~asu_flags[0] & {{(width-1){1'b0}}, 1'b1}; end
-            default: begin OUT_1 = {(2**width){1'b0}}; flags = asu_flags; end
+            default: begin OUT_1 = {(2**width){1'b0}}; end
         endcase
+        asu_flags[2] = OUT_1 == 0;
+        flags = asu_flags;
     end
 endmodule
 `endif

ModelSim/alu.sv.bak

@@ -0,0 +1,20 @@
+`include "asu.v"
+`include "lu.v"
+
+// flags[0:0] = Cout
+// flags[1:1] = Overflow
+module alu #(width=8)(input logic [3:0] op,
+    input logic [width-1:0] A, input logic [width-1:0] B.
+    output logic [width-1:0] OUT_1, output logic flags[1:0]);
+
+    logic [width-1:0] asu_out;
+    logic [1:0] asu_flags;
+    logic [0:0] asu_op;
+    asu #(width) adder_unit(asu_op, A, B, asu_out, asu_flags[0], asu_flags[1]);
+
+    logic [width-1:0] lu_out;
+    lu #(width) logic_unit(op[1:0], A, B, lu_out);
+
+    // Cout = asu_flags[0]
+    // Overflow = asu_flags[0] ^ asu_flags[1]
+endmodule

ModelSim/assignment2.sv

@@ -0,0 +1,114 @@
+`ifndef ASS_2_SV
+`define ASS_2_SV
+
+`include "rom.sv"
+`include "ram.sv"
+`include "register_file.sv"
+`include "instruction_counter.sv"
+`include "control_unit.sv"
+`include "alu.sv"
+`include "shifter.sv"
+`include "sign_extender.sv"
+`include "seven_seg_4digit.sv"
+
+
+module assignment2 #(width=5, ramsz=9, romsz=10) (
+	input logic [0:0] clk, input logic [0:0] rst
+`ifdef QUARTUS_SYNTH
+    ,
+	input logic [4:0] HID_Register,
+	input logic [0:0] HID_PC,
+	input logic [0:0] HID_Hi_Low,
+	
+	output logic[7:0] out_seg_0,
+	output logic[7:0] out_seg_1,
+	output logic[7:0] out_seg_2,
+	output logic[7:0] out_seg_3
+`endif
+	);
+	// Intermediate for displaying high / low of PC or Register
+	logic[15:0] PC_Reg_Display;
+	
+	// Program / Instruction Counter Intermediates
+	logic [2**width-1:0] pc_addr;
+	logic [2**width-1:0] pc_addr_write;
+	logic [0:0] pc_we;
+	logic [2**width-1:0] instruction;
+	
+	// Instruction Classifier Intermediates
+	logic [0:0] M2R;
+	logic [0:0] M2W;
+    logic [0:0] B;
+    logic [3:0] ALU_FN;
+	logic [0:0] ALU_SRC;
+    logic [0:0] RDST;
+	logic [0:0] RW;
+		
+	// Register File intermediates
+	logic [2:0] flags;
+	logic [2**width-1:0] rs;
+	logic [2**width-1:0] rt;
+	logic [2**width-1:0] rd;
+	logic [0:0] rd_we;
+	logic [31:0] regs_out [32];
+
+    // ALU intermediates
+	logic [2**width-1:0] rd_alu;
+	logic [2**width-1:0] rt_alu;
+	
+	instruction_counter #(width) PC (clk, rst, pc_we, pc_addr_write, pc_addr);
+	
+	rom #(romsz, width) ROM (pc_addr, instruction);
+
+	logic [2**width-1:0] rd_mem;
+	ram #(ramsz, width) RAM (clk, rst, rd_alu, M2W, rt, rd_mem);
+	
+	control_unit CONTROL_UNIT (instruction[31:26], instruction[5:0],
+		M2R, M2W, B, ALU_FN, ALU_SRC, RDST, RW
+	);
+
+
+	register_file #(width, 5) REGS (
+		clk, rd_we, 
+		(RDST) ? instruction[15:11] : instruction[20:16], rd,
+		instruction[25:21], rs,
+		instruction[20:16], rt, 
+		regs_out
+   );
+    // Always use sign-extension
+    logic [2**width-1:0] rt_imm;
+    sign_extender #(4, width) SIGNEXT(1'b1, instruction[15:0], rt_imm);
+
+	alu #(width) ALU (ALU_FN, rs, rt_alu, rd_alu, flags);
+    assign rt_alu = (ALU_SRC) ? (rt_imm) : (rt);
+
+	assign pc_we = B & flags[2];
+	assign pc_addr_write = (rt_imm << 2) + pc_addr;
+	assign rd_we = RW;
+	assign rd = (M2R) ? rd_mem : rd_alu;
+
+
+`ifdef QUARTUS_SYNTH
+	// Temporary Test output
+	// assign PC_Reg_Display = 16'hC342;
+	// assign PC_Reg_Display = (HID_Hi_Low) ? regs_out[HID_Register][31:16] : regs_out[HID_Register][15:0];
+	always_comb begin
+		if (HID_PC == 1'b1) begin
+			PC_Reg_Display = (HID_Hi_Low) ? pc_addr[31:16] : pc_addr[15:0];
+		end
+		else begin
+			PC_Reg_Display = (HID_Hi_Low) ? regs_out[HID_Register][31:16] : regs_out[HID_Register][15:0];
+		end	
+	end
+	
+	seven_seg_4digit display (
+		.num(PC_Reg_Display),
+		.segments0(out_seg_0),
+		.segments1(out_seg_1),
+		.segments2(out_seg_2),
+		.segments3(out_seg_3)
+	);
+`endif // code for board test outputs only
+
+endmodule
+`endif

ModelSim/assignment2.sv.bak

@@ -0,0 +1,19 @@
+`include "rom.sv"
+`include "ram.sv"
+`include "instruction_counter.sv"
+`include "instruction_classifier.sv"
+`include "alu.sv"
+
+
+module assignment2 #(width=5, ramsz=9, romsz=10) (input logic [0:0] clk);
+    
+    logic [romsz-1:0] pc_addr;
+    logic [0:0] pc_we;
+    logic [2**width-1:0] instruction;
+
+    instruction_counter pc #(romsz)(clk, pc_we, pc_addr, pc_addr);
+    ROM rom #(romsz, 2**width)();
+    RAM ram #(ramsz,  2**width)();
+    alu alu #(width)();
+
+endmodule

ModelSim/assignment3.sv

@@ -0,0 +1,95 @@
+`ifndef ASS_3_SV
+`define ASS_3_SV
+
+`include "rom.sv"
+`include "ram.sv"
+`include "register_file.sv"
+`include "instruction_counter.sv"
+`include "control_unit.sv"
+`include "alu.sv"
+`include "shifter.sv"
+`include "sign_extender.sv"
+`include "gatereg.sv"
+
+module assignment3 #(width=5, romsz=9, ramsz=10)(
+	input logic [0:0] clk, input logic [0:0] rst
+	);
+	logic [31:0] regs_out [32];
+	logic [2**width-1:0] pc_addr, pc_addr_2;
+	logic [2**width-1:0] pc_addr_write;
+	logic [0:0] pc_we;
+	// TODO: Verify if we need a clk gating on pc_addr
+	instruction_counter #(width) PC (clk, rst, pc_we, pc_addr_write, pc_addr);
+	gatereg #(width, 2) gate_pc_addr_1(clk, rst, 1'b1, pc_addr, pc_addr_2);
+
+
+	logic [2**width-1:0] rom_rd;
+	logic [2**width-1:0] rom_addr;
+	logic [2**width-1:0] instruction, instruction_1;
+	rom #(romsz, width) ROM (rom_addr[romsz-1:0], rom_rd);
+	gatereg #(width, 1) gate_pc_addr(clk, rst, 1'b1, pc_addr, rom_addr);
+	gatereg #(width, 1) gate_instruction(clk, rst, 1'b1, rom_rd, instruction);
+	gatereg #(width, 1) gate_instruction_1(clk, rst, 1'b1, instruction, instruction_1);
+
+
+	logic [0:0] cu_m2r, cu_m2w, cu_b, cu_alu_src, cu_rdst, cu_rw;
+	logic [3:0] cu_alu_fn, ALU_FN;
+	logic [0:0] B, MEM_WE, RDST, ALU_SRC, REG_WE, REGW_MEM_OR_RD;
+	control_unit CONTROL_UNIT (instruction[31:26], instruction[5:0],
+		cu_m2r, cu_m2w, cu_b, cu_alu_fn, cu_alu_src, cu_rdst, cu_rw
+	);
+	gatereg #(0, 1) gate_cu_rdst (clk, rst, 1'b1, cu_rdst, RDST);
+	gatereg #(0, 1) gate_cu_alu_src (clk, rst, 1'b1, cu_alu_src, ALU_SRC);
+	gatereg #(2, 1) gate_cu_alu_fn (clk, rst, 1'b1, cu_alu_fn, ALU_FN);
+
+	gatereg #(0, 2) gate_cu_b (clk, rst, 1'b1, cu_b, B);
+	gatereg #(0, 2) gate_cu_m2w (clk, rst, 1'b1, cu_m2w, MEM_WE);
+	
+	gatereg #(0, 3) gate_cu_rw (clk, rst, 1'b1, cu_rw, REG_WE);
+	gatereg #(0, 3) gate_cu_m2r (clk, rst, 1'b1, cu_m2r, REGW_MEM_OR_RD);
+	
+	logic [2**width-1:0] regf_rs, regf_rs_1;
+	logic [2**width-1:0] regf_rt, regf_rt_1, regf_rt_2;
+	logic [7:0] regf_a3, regf_a3_2;
+	logic [2**width-1:0] rd, rd_mem, rd_alu;
+	assign rd = (REGW_MEM_OR_RD) ? rd_mem : rd_alu;
+	assign regf_a3 = (RDST) ? instruction_1[15:11] : instruction_1[20:16];
+	// TODO: Connect inputs
+	gatereg #(3, 2) gate_regf_a3 (clk, rst, 1'b1, regf_a3, regf_a3_2);
+	register_file #(width, 5) REGS (
+		~clk, REG_WE, 
+		regf_a3_2[4:0], rd,
+		instruction[25:21], regf_rs,
+		instruction[20:16], regf_rt,
+		regs_out
+	);
+	gatereg #(width, 1) gate_regf_rs(clk, rst, 1'b1, regf_rs, regf_rs_1);
+	gatereg #(width, 1) gate_regf_rt(clk, rst, 1'b1, regf_rt, regf_rt_1);
+	gatereg #(width, 1) gate_regf_rt_1(clk, rst, 1'b1, regf_rt_1, regf_rt_2);
+	
+	logic [2**width-1:0] sign_ext_imm, rt_imm;
+	sign_extender #(4, width) SIGNEXT(1'b1, instruction[15:0], sign_ext_imm);
+	gatereg #(width, 1) gate_sign_ext_imm(clk, rst, 1'b1, sign_ext_imm, rt_imm);
+
+
+	logic [2**width-1:0] alu_out, alu_out_1, alu_out_2;
+	logic [3:0] alu_flags, alu_flags_1;
+	alu #(width) ALU (ALU_FN, regf_rs_1, (ALU_SRC) ? rt_imm : regf_rt_1, alu_out, alu_flags);
+	gatereg #(width, 1) gate_alu_out (clk, rst, 1'b1, alu_out, alu_out_1);
+	gatereg #(width, 1) gate_alu_out_1 (clk, rst, 1'b1, alu_out_1, alu_out_2);
+	gatereg #(width, 1) gate_alu_flags (clk, rst, 1'b1, alu_flags, alu_flags_1);
+	assign rd_alu = alu_out_2;
+
+	logic [2**width-1:0] new_pc_addr, new_pc_addr_1;
+	assign new_pc_addr = (rt_imm << 2) + pc_addr_2;
+	gatereg #(width, 1) gate_new_pc_addr (clk, rst, 1'b1, new_pc_addr, new_pc_addr_1);
+	
+
+	assign pc_addr_write = new_pc_addr_1;
+	assign pc_we = B & alu_flags_1[2];
+	logic [2**width-1:0] mem_out, mem_out_1;
+	ram #(ramsz, width) RAM (clk, rst, alu_out_1, MEM_WE, regf_rt_2, mem_out);
+	gatereg #(width, 1) gate_mem_out (clk, rst, 1'b1, mem_out, mem_out_1);
+	assign rd_mem = mem_out_1;
+endmodule
+`endif

ModelSim/assignment3.sv.bak

@@ -0,0 +1,95 @@
+`ifndef ASS_3_SV
+`define ASS_3_SV
+
+`include "rom.sv"
+`include "ram.sv"
+`include "register_file.sv"
+`include "instruction_counter.sv"
+`include "control_unit.sv"
+`include "alu.sv"
+`include "shifter.sv"
+`include "sign_extender.sv"
+`include "gatereg.sv"
+
+module assignment3 #(width=5, romsz=9, ramsz=10)(
+    input logic [0:0] clk, input logic [0:0] rst
+	);
+	logic [31:0] regs_out [32];
+	logic [2**width-1:0] pc_addr, pc_addr_2;
+	logic [2**width-1:0] pc_addr_write;
+	logic [0:0] pc_we;
+	// TODO: Verify if we need a clk gating on pc_addr
+	instruction_counter #(width) PC (clk, rst, pc_we, pc_addr_write, pc_addr);
+	gatereg #(width, 2) gate_pc_addr_1(clk, rst, 1'b1, pc_addr, pc_addr_2);
+
+
+	logic [2**width-1:0] rom_rd;
+	logic [2**width-1:0] rom_addr;
+	logic [2**width-1:0] instruction, instruction_1;
+	rom #(romsz, width) ROM (rom_addr[romsz-1:0], rom_rd);
+	gatereg #(width, 1) gate_pc_addr(clk, rst, 1'b1, pc_addr, rom_addr);
+	gatereg #(width, 1) gate_instruction(clk, rst, 1'b1, rom_rd, instruction);
+	gatereg #(width, 1) gate_instruction_1(clk, rst, 1'b1, instruction, instruction_1);
+
+
+	logic [0:0] cu_m2r, cu_m2w, cu_b, cu_alu_src, cu_rdst, cu_rw;
+	logic [3:0] cu_alu_fn, ALU_FN;
+	logic [0:0] B, MEM_WE, RDST, ALU_SRC, REG_WE, REGW_MEM_OR_RD;
+	control_unit CONTROL_UNIT (instruction[31:26], instruction[5:0],
+		cu_m2r, cu_m2w, cu_b, cu_alu_fn, cu_alu_src, cu_rdst, cu_rw
+	);
+	gatereg #(0, 1) gate_cu_rdst (clk, rst, 1'b1, cu_rdst, RDST);
+	gatereg #(0, 1) gate_cu_alu_src (clk, rst, 1'b1, cu_alu_src, ALU_SRC);
+	gatereg #(2, 1) gate_cu_alu_fn (clk, rst, 1'b1, cu_alu_fn, ALU_FN);
+
+	gatereg #(0, 2) gate_cu_b (clk, rst, 1'b1, cu_b, B);
+	gatereg #(0, 2) gate_cu_m2w (clk, rst, 1'b1, cu_m2w, MEM_WE);
+	
+	gatereg #(0, 3) gate_cu_rw (clk, rst, 1'b1, cu_rw, REG_WE);
+	gatereg #(0, 3) gate_cu_m2r (clk, rst, 1'b1, cu_m2r, REGW_MEM_OR_RD);
+	
+	logic [2**width-1:0] regf_rs, regf_rs_1;
+	logic [2**width-1:0] regf_rt, regf_rt_1, regf_rt_2;
+	logic [7:0] regf_a3, regf_a3_2;
+	logic [2**width-1:0] rd, rd_mem, rd_alu;
+	assign rd = (REGW_MEM_OR_RD) ? rd_mem : rd_alu;
+	assign regf_a3 = (RDST) ? instruction_1[15:11] : instruction_1[20:16];
+	// TODO: Connect inputs
+	gatereg #(3, 2) gate_regf_a3 (clk, rst, 1'b1, regf_a3, regf_a3_2);
+	register_file #(width, 5) REGS (
+		~clk, REG_WE, 
+		regf_a3_2[4:0], rd,
+		instruction[25:21], regf_rs,
+		instruction[20:16], regf_rt,
+		regs_out
+	);
+	gatereg #(width, 1) gate_regf_rs(clk, rst, 1'b1, regf_rs, regf_rs_1);
+	gatereg #(width, 1) gate_regf_rt(clk, rst, 1'b1, regf_rt, regf_rt_1);
+	gatereg #(width, 1) gate_regf_rt_1(clk, rst, 1'b1, regf_rt_1, regf_rt_2);
+	
+	logic [2**width-1:0] sign_ext_imm, rt_imm;
+	sign_extender #(4, width) SIGNEXT(1'b1, instruction[15:0], sign_ext_imm);
+	gatereg #(width, 1) gate_sign_ext_imm(clk, rst, 1'b1, sign_ext_imm, rt_imm);
+
+
+	logic [2**width-1:0] alu_out, alu_out_1, alu_out_2;
+	logic [3:0] alu_flags, alu_flags_1;
+	alu #(width) ALU (ALU_FN, regf_rs_1, (ALU_SRC) ? rt_imm : regf_rt_1, alu_out, alu_flags);
+	gatereg #(width, 1) gate_alu_out (clk, rst, 1'b1, alu_out, alu_out_1);
+	gatereg #(width, 1) gate_alu_out_1 (clk, rst, 1'b1, alu_out_1, alu_out_2);
+	gatereg #(width, 1) gate_alu_flags (clk, rst, 1'b1, alu_flags, alu_flags_1);
+	assign rd_alu = alu_out_2;
+
+	logic [2**width-1:0] new_pc_addr, new_pc_addr_1;
+	assign new_pc_addr = (rt_imm << 2) + pc_addr_2;
+	gatereg #(width, 1) gate_new_pc_addr (clk, rst, 1'b1, new_pc_addr, new_pc_addr_1);
+	
+
+	assign pc_addr_write = new_pc_addr_1;
+	assign pc_we = B & alu_flags_1[2];
+	logic [2**width-1:0] mem_out, mem_out_1;
+	ram #(ramsz, width) RAM (clk, rst, alu_out_1, MEM_WE, regf_rt_2, mem_out);
+	gatereg #(width, 1) gate_mem_out (clk, rst, 1'b1, mem_out, mem_out_1);
+	assign rd_mem = mem_out_1;
+endmodule
+`endif

ModelSim/asu.sv

@@ -4,9 +4,11 @@
 module asu #(parameter width = 2)(
 	input logic [0:0] op,
 	input logic[2**width-1:0] A, input logic[2**width-1:0] B,
-   output logic[2**width-1:0] OUT_1, output logic[0:0] COUT, output logic[0:0] OUT_CIN);
+    output logic[2**width-1:0] OUT_1, output logic[0:0] COUT, output logic[0:0] OUT_CIN
+    );
 
     logic [2**width-1:0] operand;
+
     always_comb begin
         // A + (sub) ? B : -B
         // Adds an extra bit to all operands to calculate the carry bit. Not optimal for hardware synthesis
@@ -18,5 +20,6 @@ module asu #(parameter width = 2)(
     // Need to do this outside of the always_comb block because parameter-based bitslicing/indexing isn't supported?
     // Cin for final bit in adder to later be xor'ed with COUT to determine if a signed overflow occured for the MIPS architecture
     assign OUT_CIN = A[2**width-1] ^ operand[2**width-1] ^ OUT_1[2**width-1];
+
 endmodule
 `endif

ModelSim/asu.sv.bak

@@ -0,0 +1,16 @@
+module asu #(width=8)(input logic [0:0] op,
+    input logic[width-1:0] A, input logic[width-1:0] B,
+    output logic[width-1:0] OUT_1, output logic[0:0] COUT, output logic[0:0] OUT_CIN);
+
+    logic [width-1:0] operand;
+    always_comb begin
+        // A + (sub) ? B : -B
+        // Adds an extra bit to all operands to calculate the carry bit. Not optimal for hardware synthesis
+        operand = (B ^ {(width){op}});
+        {COUT, OUT_1} = A + operand + {{(width-1){1'b0}}, op};
+    end
+
+    // Need to do this outside of the always_comb block because parameter-based bitslicing/indexing isn't supported?
+    // Cin for width-2'th bit to later be xor'ed with COUT to determine if a signed overflow occured for the MIPS architecture
+    assign OUT_CIN = A[width-1] ^ operand[width-1] ^ OUT_1[width-1];
+endmodule

ModelSim/control_unit.sv

@@ -0,0 +1,36 @@
+`ifndef CONTROL_UNIT_H
+`define CONTROL_UNIT_H
+`include "instruction_classifier.sv"
+
+module control_unit (
+    input logic [5:0] op, input logic [5:0] func,
+    output logic [0:0] M2R,     //  Enables writing data stored in memory at the address (rs/A)+(ALU_SRC ? imm : rt/B) into rd
+    output logic [0:0] M2W,     //  Enable writing data stored in rt/B into memory at the address (rs/A)+(ALU_SRC ? imm : rt/B)
+    output logic [0:0] B,       //  AND'ed with flags to determine if branch is permitted
+    output logic [3:0] ALU_FN,  //  Controls what function the ALU is to perform
+    output logic [0:0] ALU_SRC, //  Controls whether to use the rt/B register read port or 16-bit immediate 
+    output logic [0:0] RDST,    //  Controls where to look in the instruction encoding for the register write address
+    output logic [0:0] RW       //  Enable register write port
+);
+    logic [0:0] TYPE_R;
+    logic [0:0] TYPE_B1;
+    logic [0:0] TYPE_J;
+    logic [0:0] TYPE_B2;
+    logic [0:0] TYPE_I;
+    logic [0:0] TYPE_F;
+    logic [0:0] TYPE_M;
+
+    instruction_classifier CLASSIFIER (op, TYPE_R, TYPE_B1, TYPE_J, TYPE_B2, TYPE_I, TYPE_F, TYPE_M);
+
+    always_comb begin
+        M2R = TYPE_M & ~((op & 6'b001000) >> 3);
+        M2W = TYPE_M & ((op & 6'b001000) >> 3);
+        B = TYPE_B1 | TYPE_B2 | TYPE_J;
+        ALU_FN = (func & {(4){TYPE_R}}) | ( {2'b00, (op & 6'b000011)} & {(4){TYPE_I}}) | (4'b0010 & {4{TYPE_B1 | TYPE_B2}});
+        ALU_SRC = TYPE_I | TYPE_M;
+        RDST = TYPE_R;  // Imm ops store back into rt
+        RW = TYPE_R | TYPE_I | M2R;
+    end
+
+endmodule
+`endif

ModelSim/gatereg.sv

@@ -0,0 +1,21 @@
+module gatereg #(width, ndelay=1)(
+    input logic [0:0] clk, input logic [0:0] rst, input logic [0:0] en,
+    input logic [2**width-1:0] in, output logic [2**width-1:0] out
+);
+    logic [2**width-1:0] hold_value[ndelay];
+
+    assign out = hold_value[ndelay-1];
+    always_ff @( posedge clk ) begin
+        if (rst) begin
+            for (integer i = 0; i < ndelay; ++i) begin
+                hold_value[i] <= {(2**width){1'b0}};
+            end
+        end else if (en) begin
+            hold_value[0] <= in;
+            for (integer i = 1; i < ndelay; ++i) begin
+                hold_value[i] <= hold_value[i-1];
+            end
+        end
+    end
+
+endmodule

ModelSim/hazard_unit.sv

@@ -0,0 +1,84 @@
+`ifndef HAZARD_SV
+`define HAZARD_SV
+
+module hazard_unit (
+    // (I)Decode/EXecute stage
+    input  logic        idex_MemRead,
+    input  logic [4:0]  idex_Rt,
+    input  logic [4:0]  idex_Rs,
+
+    // EXecute/MEMory stage
+    input  logic        exmem_RegWrite,
+    input  logic [4:0]  exmem_Rd,
+
+    // MEMory/WriteBack stage
+    input  logic        memwb_RegWrite,
+    input  logic [4:0]  memwb_Rd,
+
+    // (I)Fetch/(I)Decode stage
+    input  logic [4:0]  ifid_Rs,
+    input  logic [4:0]  ifid_Rt,
+
+    // branch / jump control
+    input  logic        branch_taken,
+    input  logic        jump_taken,
+
+    // outputs
+    output logic [1:0]  forwardA,
+    output logic [1:0]  forwardB,
+    output logic        stallF, // Stall OC register
+    output logic        stallD, // Stall Instruction Memory
+    output logic        flushE, // Flush ALU inputs
+    output logic        flushD  // Flush
+);
+
+    // Forwarding encoding:
+    // 00 = no forwarding
+    // 01 = forward from MEM/WB
+    // 10 = forward from EX/MEM
+
+    always_comb begin
+        // defaults
+        forwardA = 2'b00;
+        forwardB = 2'b00;
+        stallF   = 1'b0;
+        stallD   = 1'b0;
+        flushE   = 1'b0;
+        flushD   = 1'b0;
+
+        // Forwarding for ALU src A
+        if (exmem_RegWrite && (exmem_Rd != 5'd0) && (exmem_Rd == idex_Rs))
+            forwardA = 2'b10;
+        else if (memwb_RegWrite && (memwb_Rd != 5'd0) && (memwb_Rd == idex_Rs))
+            forwardA = 2'b01;
+
+        // Forwarding for ALU src B
+        if (exmem_RegWrite && (exmem_Rd != 5'd0) && (exmem_Rd == idex_Rt))
+            forwardB = 2'b10;
+        else if (memwb_RegWrite && (memwb_Rd != 5'd0) && (memwb_Rd == idex_Rt))
+            forwardB = 2'b01;
+
+        // -------------------------
+        // Load-use hazard stall
+        // if instruction in EX is a load and
+        // next instruction uses its result
+        // -------------------------
+        if (idex_MemRead &&
+            ((idex_Rt == ifid_Rs) || (idex_Rt == ifid_Rt))) begin
+            stallF = 1'b1;
+            stallD = 1'b1;
+            flushE = 1'b1;   // insert bubble into EX
+        end
+
+        // -------------------------
+        // Control hazard flush
+        // branch/jump resolved in EX
+        // -------------------------
+        if (branch_taken || jump_taken) begin
+            flushD = 1'b1;   // flush wrong instruction in decode
+            flushE = 1'b1;   // flush wrong instruction in execute
+        end
+    end
+
+endmodule
+`endif

ModelSim/instruction_counter.sv

@@ -0,0 +1,24 @@
+`ifndef INSTRUCTION_COUNTER_H
+`define INSTRUCTION_COUNTER_H
+
+module instruction_counter #(parameter width=5)(
+    input logic [0:0] clk, input logic [0:0] rst, input logic [0:0] we,
+    input logic [2**width-1:0] W,
+    output logic [2**width-1:0] addr
+);
+
+    logic [2**width-1:0] pc;
+    
+    always_ff @(posedge clk or posedge rst) begin
+        if (rst) begin
+            pc <= {(2**width){1'b0}};
+        end else if (we) begin
+            pc <= W;
+        end else begin
+            pc <= pc + 4;
+        end
+    end
+
+    assign addr = pc;
+endmodule
+`endif

ModelSim/lu.sv

@@ -1,13 +1,13 @@
 `ifndef LU_H_SV
 `define LU_H_SV
 module lu #(parameter width = 2) (
-    input logic [1:0] op,
+    input logic [1:0] op,           // 2 bit operand
-    input logic [2**width-1:0] A,
+    input logic [2**width-1:0] A,  // width defined as 2^n 
 	 input logic [2**width-1:0] B,
     output logic [2**width-1:0] Y);
 	 
     always_comb begin
-		case (op)
+		case (op) // different operations of A and B based on operand
 			2'b00:	Y =   A & B;
 			2'b01:	Y =   A | B;
 			2'b10:	Y =   A ^ B;

ModelSim/lu.sv.bak

@@ -0,0 +1,12 @@
+module lu #(width=8) (
+    input logic [1:0] op,
+    input logic [width-1:0] A, input logic [width-1:0] B,
+    output logic [width-1:0] OUT_1);
+
+    always_comb begin
+        if      (op == 2'b00) OUT_1 =   A & B;
+        else if (op == 2'b01) OUT_1 =   A | B;
+        else if (op == 2'b10) OUT_1 =   A ^ B;
+        else if (op == 2'b10) OUT_1 = ~(A | B);
+    end
+endmodule

ModelSim/mips.sv

@@ -0,0 +1,123 @@
+`include "assignment2.sv"
+
+`timescale 1us/10ns
+
+`define PRINT_REGISTERS(regs)\
+    $display("\tt0-t8: \t0x%0x 0x%0x 0x%0x 0x%0x 0x%0x 0x%0x 0x%0x 0x%0x\n\ts0-s8: \t0x%0x 0x%0x 0x%0x 0x%0x 0x%0x 0x%0x 0x%0x 0x%0x\n",\
+        regs[8], regs[9], regs[10], regs[11], regs[12], regs[13], regs[14], regs[15],   \
+        regs[16], regs[17], regs[18], regs[19], regs[20], regs[21], regs[22], regs[23]  \
+    );
+`define TEST_CHECK(cond) if (cond) begin end else begin   \
+        $display("Check %s failed", `"cond`");            \
+        `PRINT_REGISTERS(CPU.REGS.regs);                  \
+        num_errors += 1;                                  \
+    end
+
+module mips_tb();
+    logic [0:0] clk;
+    logic [0:0] rst;
+    assignment2 #(5) CPU (clk, rst);
+
+    initial clk = 0;
+    initial rst = 0;
+    always #1 clk = ~clk;
+
+    integer num_errors = 0;
+    initial begin
+        rst = 1;
+        #2;
+        rst = 0;
+        #2;
+
+        $dumpfile("output.vcd");
+		$dumpvars(0, clk);
+		$dumpvars(1, CPU.REGS);
+		$dumpvars(2, CPU.ROM);
+		$dumpvars(3, CPU.PC);
+		$dumpvars(4, CPU.pc_addr);
+		$dumpvars(5, CPU.CONTROL_UNIT);
+		$dumpvars(5, CPU.instruction);
+		$dumpvars(5, CPU.ALU);
+		$dumpvars(6, CPU.flags);
+
+        // Zero out lower registers
+        $display("Beginning MIPS tests");
+
+        // Check R-type / initialise
+        #2;
+        `TEST_CHECK(CPU.REGS.regs[8] == 32'd0);
+        #2;
+        `TEST_CHECK(CPU.REGS.regs[9] == (CPU.REGS.regs[8] + 32'd7));
+
+        // Check load-store
+        #2;
+        `TEST_CHECK(CPU.RAM.mem[0] == CPU.REGS.regs[9]);
+        #2;
+        `TEST_CHECK(CPU.REGS.regs[10] == CPU.RAM.mem[0]);
+
+        // Check arithmetic
+        #2;
+        `TEST_CHECK(CPU.REGS.regs[11] == (CPU.REGS.regs[9] + CPU.REGS.regs[10]));
+        #2;
+        `TEST_CHECK(CPU.REGS.regs[12] == (CPU.REGS.regs[9] - CPU.REGS.regs[11]));
+        #2;
+        `TEST_CHECK(CPU.REGS.regs[13] == (CPU.REGS.regs[9] + 3));
+        #2;
+        `TEST_CHECK(CPU.REGS.regs[14] == (CPU.REGS.regs[12] + CPU.REGS.regs[13]));
+
+        // Check logic instructions
+        #2;
+        `TEST_CHECK(CPU.REGS.regs[16] == (CPU.REGS.regs[9] & CPU.REGS.regs[13]));
+        #2;
+        `TEST_CHECK(CPU.REGS.regs[17] == (CPU.REGS.regs[9] | CPU.REGS.regs[13]));
+        #2;
+        `TEST_CHECK(CPU.REGS.regs[18] == (CPU.REGS.regs[9] ^ CPU.REGS.regs[13]));
+        #2;
+        `TEST_CHECK(CPU.REGS.regs[19] == ( ~(CPU.REGS.regs[9] | CPU.REGS.regs[13]) ));
+
+        // Check SLT instructions
+        #2;
+        `TEST_CHECK(CPU.REGS.regs[20] == $signed(CPU.REGS.regs[12]) < $signed(CPU.REGS.regs[14]));
+        #2;
+        `TEST_CHECK(CPU.REGS.regs[21] == $unsigned(CPU.REGS.regs[12]) < $unsigned(CPU.REGS.regs[14]));
+        
+        // Check loop branching
+        #2;
+        for (integer N = 1; N < 11; ++N) begin
+            #2;
+            `TEST_CHECK(CPU.REGS.regs[8] == 32'(N));
+            
+            #2;
+            `TEST_CHECK(CPU.REGS.regs[22] == $unsigned(CPU.REGS.regs[8]) < $unsigned(CPU.REGS.regs[13]));
+            if (N < 10)
+                #2;
+            #2;
+        end
+
+        // Final state check
+        #2;
+        `TEST_CHECK(CPU.REGS.regs[8]  == 32'd10);
+        `TEST_CHECK(CPU.REGS.regs[9]  == 32'd7);
+        `TEST_CHECK(CPU.REGS.regs[10] == 32'd7);
+        `TEST_CHECK(CPU.REGS.regs[11] == 32'd14);
+        `TEST_CHECK(CPU.REGS.regs[12] == -32'sd7);
+        `TEST_CHECK(CPU.REGS.regs[13] == 32'd10);
+        `TEST_CHECK(CPU.REGS.regs[14] == 32'd3);
+        `TEST_CHECK(CPU.REGS.regs[15] == 32'd0);
+        
+        `TEST_CHECK(CPU.REGS.regs[16] == 32'd2);
+        `TEST_CHECK(CPU.REGS.regs[17] == 32'd15);
+        `TEST_CHECK(CPU.REGS.regs[18] == 32'd13);
+        `TEST_CHECK(CPU.REGS.regs[19] == -32'sd16);
+        `TEST_CHECK(CPU.REGS.regs[20] == 32'd1);
+        `TEST_CHECK(CPU.REGS.regs[21] == 32'd0);
+        `TEST_CHECK(CPU.REGS.regs[22] == 32'd0);
+        `TEST_CHECK(CPU.REGS.regs[23] == 32'd0);
+
+        if (num_errors == 0) begin $display("\x1b[38;5;10mAll MIPS tests passing\x1b[m");
+        end else begin $display("\x1b[38;5;9m%0d MIPS test(s) failing\x1b[m", num_errors); end
+
+        $dumpflush;
+        $finish;
+    end
+endmodule

ModelSim/ram.sv

@@ -0,0 +1,28 @@
+`ifndef RAM_H
+`define RAM_H
+
+module ram #(addrwidth=9, datawidth=5)(
+    input logic [0:0] clk, input logic [0:0] rst,
+    input logic [addrwidth-1:0] addr,
+    input logic [0:0] we,
+    input logic [2**datawidth-1:0] data_in,
+    output logic [2**datawidth-1:0] data_out
+);
+
+    // TODO: Make this byte-sized, NOT word-sized!
+    logic [2**datawidth-1:0] mem[0:255];
+
+    always_ff @(posedge clk) begin
+        if (rst) begin
+            for (integer ADDR = 0; ADDR < 256; ADDR = ADDR + 1) begin
+                mem[ADDR] <= 32'b0;
+            end
+        end else if (we) begin
+            mem[addr] <= data_in;
+        end
+    end
+    assign data_out = mem[addr];
+
+endmodule
+
+`endif

ModelSim/register_file.sv

@@ -0,0 +1,29 @@
+`ifndef REGISTER_FILE_H
+`define REGISTER_FILE_H
+
+module register_file #(parameter width=5, parameter nregs=5)(
+    input logic [0:0] clk, input logic[0:0] we,
+    input logic [nregs-1:0] WA, input logic [2**width-1:0] WD,
+    input logic [nregs-1:0] RA1, output logic [2**width-1:0] RD1,
+    input logic [nregs-1:0] RA2, output logic [2**width-1:0] RD2,
+    output logic [2**width-1:0] regs_out [2**nregs]
+);
+    localparam BW = 2**width;
+    logic [2**width-1:0] regs[2**nregs];
+
+    initial begin
+        for (integer N = 0; N < (2**nregs); ++N)
+            regs[N] = 32'd0;
+    end
+
+    always_ff @(posedge clk) begin
+        if (we & (WA != {(2**width){1'b0}} )) begin
+            regs[WA] <= WD;
+        end
+    end
+
+    assign RD1 = regs[RA1];
+    assign RD2 = regs[RA2];
+    assign regs_out = regs;  // Expose registers externally
+endmodule
+`endif

ModelSim/rom.sv

@@ -0,0 +1,24 @@
+`ifndef ROM_H
+`define ROM_H
+
+module rom #(parameter m=7,p=4) (
+        input logic [m-1:0] Ad,
+        output logic [2**p-1:0] Dout
+    );
+    
+    logic [2**p-1:0] mem[2**m];
+    assign Dout = mem[Ad>>2];   // Because word-size versus byte size hack
+
+    //Load the program in memory
+    // The machine code stored in text file program.dat written in Hex format
+    initial begin
+        `ifdef QUARTUS_SYNTH
+            $readmemh("../../asm/bin/ELEC4720-2026s2-Ass-02-Demo.hex", mem, 0, 2**m-1); //$readmemb for binary
+        `else
+            $readmemh("./asm/bin/ELEC4720-2026s2-Ass-02-Demo.hex", mem, 0, 2**m-1); //$readmemb for binary
+        `endif
+    end
+endmodule // end rom module
+
+`endif
+

ModelSim/rom.sv.bak

@@ -0,0 +1,24 @@
+`ifndef ROM_H
+`define ROM_H
+
+module rom #(parameter m=7,p=4) (
+        input logic [m-1:0] Ad,
+        output logic [2**p-1:0] Dout
+    );
+    
+    logic [2**p-1:0] mem[2**m];
+    assign Dout = mem[Ad>>2];   // Because word-size versus byte size hack
+
+    //Load the program in memory
+    // The machine code stored in text file program.dat written in Hex format
+    initial begin
+        `ifdef QUARTUS_SYNTH
+            $readmemh("../../asm/bin/ELEC4720-2026s2-Ass-02-Demo.hex", mem, 0, 2**m-1); //$readmemb for binary
+        `else
+            $readmemh("./asm/bin/ELEC4720-2026s2-Ass-02-Demo.hex", mem, 0, 2**m-1); //$readmemb for binary
+        `endif
+    end
+endmodule // end rom module
+
+`endif
+

ModelSim/seven_seg_4digit.sv

@@ -0,0 +1,44 @@
+`ifndef SEVEN_SEG_4_H_SV
+`define SEVEN_SEG_4_H_SV
+
+`include "seven_seg.sv"
+module seven_seg_4digit (
+    input  logic [15:0] num,
+    output logic [7:0]  segments0,
+    output logic [7:0]  segments1,
+    output logic [7:0]  segments2,
+    output logic [7:0]  segments3
+);
+
+    // Rightmost digit
+    seven_seg digit0 (
+        .num(num[3:0]),
+        .rbi_inv(1'b1),
+        .segments(segments0)
+    );
+
+    // Second digit from right
+    seven_seg digit1 (
+        .num(num[7:4]),
+        .rbi_inv(1'b1),
+        .segments(segments1)
+    );
+
+    // Third digit from right
+    seven_seg digit2 (
+        .num(num[11:8]),
+        .rbi_inv(1'b1),
+        .segments(segments2)
+    );
+
+    // Leftmost digit
+    seven_seg digit3 (
+        .num(num[15:12]),
+        .rbi_inv(1'b1),
+        .segments(segments3)
+    );
+
+endmodule
+
+`endif
+

ModelSim/shifter.sv

@@ -3,7 +3,7 @@
 module shifter #(width=2)(input logic [2:0] op,
     input logic[2**width-1:0] A, input logic[2**width-1:0] B, input logic[width-1:0] C, 
     output logic[2**width-1:0] OUT_1);
-
+// A and B are 2^n bits wide and C is n bits wide as according to the docs
     always_comb begin
         case (op)
             3'b000: OUT_1 = A << C;

ModelSim/shifter.sv.bak

@@ -0,0 +1,19 @@
+`ifndef SHIFTER_H_SV
+`define SHIFTER_H_SV
+module shifter #(width=8)(input logic [2:0] op,
+    input logic[width-1:0] A, input logic[width-1:0] C, input logic[$clog2(width)-1:0] B,
+    output logic[width-1:0] OUT_1);
+
+    always_comb begin
+        case (op)
+            3'b000: OUT_1 = A << C;
+            3'b001: OUT_1 = A >> C;
+            3'b011: OUT_1 = $signed(A) >>> C;
+            3'b100: OUT_1 = A << B;
+            3'b101: OUT_1 = A >> B;
+            3'b111: OUT_1 = $signed(A) >>> B;
+            default:OUT_1 = A;
+        endcase
+    end    
+endmodule
+`endif

ModelSim/sign_extender.sv

@@ -0,0 +1,16 @@
+`ifndef SIGN_EXTENDER_H
+`define SIGN_EXTENDER_H
+
+module sign_extender #(in_width=4, out_width=5)(
+    input logic [0:0] op,
+    input logic [2**in_width-1:0] val,
+    output logic [2**out_width-1:0] ext_val
+);
+    logic [0:0] msb;
+    assign msb = (val >> (in_width-1)) & 1'b1;
+    assign ext_val = op
+        ? { {(2**out_width - 2**in_width){msb}}, val }
+        : { {(2**out_width - 2**in_width){1'b0}}, val };
+  
+endmodule
+`endif

ModelSim/transcript

@@ -1,21 +1,2 @@
-# Loading project Assignment_1_Q2
+# Loading project Assignment_2
-vsim work.lu_tb
+# Compile of hazard_unit.sv was successful.
-# vsim work.lu_tb 
-# Start time: 16:47:26 on Sep 15,2026
-# Loading sv_std.std
-# Loading work.lu_tb
-# Loading work.lu
-add wave -position end  sim:/lu_tb/op
-add wave -position end  sim:/lu_tb/A
-add wave -position end  sim:/lu_tb/B
-add wave -position end  sim:/lu_tb/C
-add wave -position end  sim:/lu_tb/C_exp
-run
-# Beginning LU tests
-run
-run
-run
-run -all
-# All LU tests passing
-# End time: 16:52:34 on Sep 15,2026, Elapsed time: 0:05:08
-# Errors: 0, Warnings: 1

ModelSim/work/_info

@@ -11,32 +11,32 @@ cModel Technology
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 Z4 d/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim
-Z5 w1789355084
+Z5 w1792115823
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-!i122 18
+!i122 215
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Quartus/A2/assignment2.qsf

@@ -121,4 +121,10 @@ set_location_assignment PIN_AC24 -to out_seg_3[5]
 set_location_assignment PIN_AC23 -to out_seg_3[6]
 
 
+set_location_assignment PIN_AC9 -to rst[0]
+set_instance_assignment -name IO_STANDARD "1.2 V" -to rst[0]
+set_location_assignment PIN_F7 -to out_seg_0[0]
+set_location_assignment PIN_F6 -to out_seg_1[0]
+set_location_assignment PIN_G6 -to out_seg_2[0]
+set_location_assignment PIN_G7 -to out_seg_3[0]
 set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top