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Fixed bug in test code where there was a hazzard, despite testing assuming no hazzard. Updated testbench to reflect this (Ln57-62).

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Added mem[0x000] to log message when printing registers.
Replaced 8 delay with explicit 5x 2 delays. (NOTE: Needed an extra one for ensuring write-back when comparing results.
Fixed bug where the wrong registers were being added together when creating the comparison point in the testbench.
Fixed testbench bug where S4 was checked twice and S5 not checked at all.
Updated display message on test failure to reflect that it is the pipelined version, not the single-cycle.
This commit is contained in:
riley committed 2026-11-05 16:15:06 +11:00
1 parent de1f346f64
commit fe53955748
3 files changed
+32 -7
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asm/bin/ELEC4720-2026s2-Ass-03-NoHazardsDemo.hex
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@@ -3,6 +3,9 @@
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asm/src/ELEC4720-2026s2-Ass-03-NoHazardsDemo.s
+3
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@@ -26,6 +26,9 @@ main:
subu $t2, $t2, $t2 # Set t2 = 0
subu $t3, $t3, $t3 # Set t3 = 0
addiu $t1, $t0, 7 # Set t1 = 7 (R9)
subu $t3, $t3, $t3 # Set t3 = 0
subu $t3, $t3, $t3 # Set t3 = 0
subu $t3, $t3, $t3 # Set t3 = 0
# Memory operations
sw $t1, 0x10000000($t0) # Save t1 to memory (change to 0x0000 for FPGA)
tests/mips_pipelined.sv
+26 -7
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@@ -3,9 +3,10 @@
`timescale 1us/10ns
`define PRINT_REGISTERS(regs)\
$display("\tt0-t8: \t0x%0x 0x%0x 0x%0x 0x%0x 0x%0x 0x%0x 0x%0x 0x%0x\n\ts0-s8: \t0x%0x 0x%0x 0x%0x 0x%0x 0x%0x 0x%0x 0x%0x 0x%0x\n",\
$display("\tt0-t8: \t0x%0x 0x%0x 0x%0x 0x%0x 0x%0x 0x%0x 0x%0x 0x%0x\n\ts0-s8: \t0x%0x 0x%0x 0x%0x 0x%0x 0x%0x 0x%0x 0x%0x 0x%0x\n\tmem[0] = 0x%0x\n",\
regs[8], regs[9], regs[10], regs[11], regs[12], regs[13], regs[14], regs[15], \
regs[16], regs[17], regs[18], regs[19], regs[20], regs[21], regs[22], regs[23] \
regs[16], regs[17], regs[18], regs[19], regs[20], regs[21], regs[22], regs[23], \
CPU.RAM.mem[0]\
);
`define TEST_CHECK(cond) if (cond) begin end else begin \
$display("Check %s failed", `"cond`"); \
@@ -29,9 +30,21 @@ module mips_pipelined_tb();
rst = 0;
#2;
$dumpfile("output.vcd");
$dumpvars(0, clk);
$dumpvars(1, CPU.REGS);
$dumpvars(2, CPU.ROM);
$dumpvars(3, CPU.RAM);
$dumpvars(4, CPU.PC);
$dumpvars(5, CPU.CONTROL_UNIT);
$dumpvars(6, CPU.ALU);
$display("Beginning Pipelined MIPS tests");
#8; // 4x steps to allow pipeline to fill up
#2; // 4x steps to allow pipeline to fill up
#2;
#2;
#2;
#2;
`TEST_CHECK(CPU.REGS.regs[8] == 32'd0);
#2;
`TEST_CHECK(CPU.REGS.regs[9] == 32'd0);
@@ -42,6 +55,12 @@ module mips_pipelined_tb();
#2;
`TEST_CHECK(CPU.REGS.regs[9] == 32'd7);
#2;
`TEST_CHECK(CPU.REGS.regs[11] == 32'd0);
#2;
`TEST_CHECK(CPU.REGS.regs[11] == 32'd0);
#2;
`TEST_CHECK(CPU.REGS.regs[11] == 32'd0);
#2;
`TEST_CHECK(CPU.RAM.mem[0] == 32'd7);
#2;
`TEST_CHECK(CPU.REGS.regs[10] == 32'd0);
@@ -58,7 +77,7 @@ module mips_pipelined_tb();
#2;
`TEST_CHECK(CPU.REGS.regs[13] == 32'd0);
#2;
`TEST_CHECK(CPU.REGS.regs[11] == (CPU.REGS.regs[10] + CPU.REGS.regs[11]) );
`TEST_CHECK(CPU.REGS.regs[11] == (CPU.REGS.regs[9] + CPU.REGS.regs[10]) );
`TEST_CHECK(CPU.REGS.regs[11] == 32'd14);
#2;
`TEST_CHECK(CPU.REGS.regs[12] == 32'd0);
@@ -97,8 +116,8 @@ module mips_pipelined_tb();
`TEST_CHECK(CPU.REGS.regs[20] == ( $signed(CPU.REGS.regs[12]) < $signed(CPU.REGS.regs[14]) ));
`TEST_CHECK(CPU.REGS.regs[20] == 32'd1);
#2;
`TEST_CHECK(CPU.REGS.regs[20] == ( CPU.REGS.regs[12] < CPU.REGS.regs[14] ));
`TEST_CHECK(CPU.REGS.regs[20] == 32'd0);
`TEST_CHECK(CPU.REGS.regs[21] == ( CPU.REGS.regs[12] < CPU.REGS.regs[14] ));
`TEST_CHECK(CPU.REGS.regs[21] == 32'd0);
// TODO: Verify program never branches
#2;
@@ -110,7 +129,7 @@ module mips_pipelined_tb();
if (num_errors == 0) begin $display("\x1b[38;5;10mAll pipelined MIPS tests passing\x1b[m");
end else begin $display("\x1b[38;5;9m%0d Single-cycle pipelined test(s) failing\x1b[m", num_errors); end
end else begin $display("\x1b[38;5;9m%0d pipelined MIPS test(s) failing\x1b[m", num_errors); end
$dumpflush;
$finish;