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riley 38fa35fccd Fixed initialisation bug and compilation error in gatereg module. Added mips_pipelined to test suite. Fixed several bugs in assignment3 MIPS module
2026-11-05 14:10:13 +11:00
asm
Added test assemblies for assignment 3 / pipelining
2026-11-04 15:42:22 +11:00
ModelSim
Added Changes to ModelSim from Modules folder (and small fix for ../hexfile path)
2026-10-16 12:59:50 +11:00
modules
Fixed initialisation bug and compilation error in gatereg module. Added mips_pipelined to test suite. Fixed several bugs in assignment3 MIPS module
2026-11-05 14:10:13 +11:00
Quartus
Repaired Sign extender module again to ensure only combinational logic used
2026-10-22 15:53:15 +11:00
Submission
Added Assignment 2 submission zip file
2026-10-16 15:09:48 +11:00
tests
Fixed initialisation bug and compilation error in gatereg module. Added mips_pipelined to test suite. Fixed several bugs in assignment3 MIPS module
2026-11-05 14:10:13 +11:00
.gitignore
Created general project structure. Only seven segment, logic unit and adder/subtractor modules and tests implemented
2026-09-03 15:25:07 +10:00
isv.py
Added python script for invoking icarus verilog. This script has three subcommands; submit, test_submit and test. test is equivalent to the run.bat shell script, submit generates a single-file verilog source suitable for submission. test_submit will run all generated submission testbenches to verify that nothing was broken.
2026-09-15 22:00:02 +10:00
README.md
Initial commit
2026-09-03 15:04:27 +10:00
run.bat
Fixed bug where includes still refered to verilog rather than systemverilog. Inverted test cases in seven segment test bench to reflect changes made to module. There is still a bug with the module where it outputs garbage
2026-09-03 16:32:56 +10:00

README.md

FPGA_Uni

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