 TroubleElectrical
|
8675f5b8ee
|
Made Assignment 2 Quartus Project
|
2026-10-13 12:04:49 +11:00 |
|
|
TroubleElectrical
|
b49e294b7d
|
Updated register_file.sv with proper naming scheme and 32bit width
|
2026-10-08 15:10:40 +11:00 |
|
|
TroubleElectrical
|
9e3525fcac
|
Added Byte addressable ROM from Slides
|
2026-10-06 16:28:23 +11:00 |
|
|
TroubleElectrical
|
3145dd6a21
|
Added ROM file from MIPS Architecture Slide Part 1
|
2026-10-06 16:03:03 +11:00 |
|
|
TroubleElectrical
|
179eb469c4
|
Removed seven segment code from alu and asu
|
2026-09-24 15:37:48 +10:00 |
|
|
TroubleElectrical
|
64cd876f12
|
Added attribution for submission files
|
2026-09-16 13:01:43 +10:00 |
|
|
TroubleElectrical
|
cbb5bb917a
|
Added Q6 submission
|
2026-09-16 12:56:48 +10:00 |
|
|
TroubleElectrical
|
ae8ac98e8d
|
Added Q5 comments and sumbission
|
2026-09-16 12:54:18 +10:00 |
|
|
TroubleElectrical
|
13f34e62c6
|
Added Q4 sumbission and comments
|
2026-09-16 12:50:58 +10:00 |
|
|
TroubleElectrical
|
7d489ab77c
|
Added Q3 sumbission and integrated all includes
|
2026-09-16 12:42:28 +10:00 |
|
|
TroubleElectrical
|
56ade6b426
|
Added comments to Logic Unit (Q2) and added to submission file
|
2026-09-16 12:38:06 +10:00 |
|
|
TroubleElectrical
|
0947f26727
|
Added comments to Q1 code and made submission file
|
2026-09-16 10:33:08 +10:00 |
|
|
TroubleElectrical
|
00167dabc8
|
Updated ModelSim Files
|
2026-09-16 10:15:08 +10:00 |
|
|
TroubleElectrical
|
afa8d9d4db
|
Enabled 2 segments for seven seg display decoder (Q1), most code just needs comments
|
2026-09-15 21:08:40 +10:00 |
|
|
TroubleElectrical
|
c27a04ef73
|
Implemented instruction classifier on board (Q6) and added blank submission files (for now)
|
2026-09-15 20:00:35 +10:00 |
|
|
TroubleElectrical
|
9583abd307
|
Updated shifter (Q5) to use proper 2**width approach and corrected the logic such that C is width bits wide, and b is 2**width (as defined in Q5 B)
|
2026-09-15 19:43:28 +10:00 |
|
|
TroubleElectrical
|
9d0c7011ce
|
Updated ALU (Q4) with 7seg and confirmed operation on board
|
2026-09-15 19:05:04 +10:00 |
|
|
TroubleElectrical
|
9e5fb6f52b
|
Updated ASU (Q3) to utilise the 7seg for output, confirmed operation of Q1 to Q3 on board
|
2026-09-15 16:52:48 +10:00 |
|
|
TroubleElectrical
|
05361dcf70
|
Added all Testbenches to Modelsim and confirmed working operation
|
2026-09-15 15:15:00 +10:00 |
|
|
TroubleElectrical
|
a73990b242
|
Added ASU (Q3) testbench to the modelsim projects folder (also confirmed operation of q2)
|
2026-09-10 15:24:44 +10:00 |
|
|
TroubleElectrical
|
dc32347c9b
|
Updated ALU code with updated 2**width approach and assigned temporary pins to ASU (Q3)
|
2026-09-09 14:27:11 +10:00 |
|
|
TroubleElectrical
|
60e5dae43b
|
Added ModelSim folder (and have to add files into it as to allow for different testbench code)
|
2026-09-08 16:32:01 +10:00 |
|
|
TroubleElectrical
|
2208eb4f16
|
Updated Q2 project and LU code such that it operates properly on the board. Changed to utilising a case statement for easier readability and also compiled and tested the code on the board.
|
2026-09-08 15:36:51 +10:00 |
|
|
TroubleElectrical
|
32eea036a8
|
Added projects for A1 q2 to q6
|
2026-09-04 13:12:33 +10:00 |
|
|
TroubleElectrical
|
3114cd6b80
|
Added the updated A1_Q1 Quartus compilation
|
2026-09-03 19:22:52 +10:00 |
|
|
TroubleElectrical
|
31a4496904
|
Including quartus prime lite edition project folders for flashing the project to the board
|
2026-09-03 16:34:31 +10:00 |
|
|
TroubleElectrical
|
41252763d4
|
Test commit
|
2026-09-03 15:12:25 +10:00 |
|