10 Commits

Include renames

Author	SHA1	Message	Date
riley	42f4e661dc	Implemented shifter and its test bench code fully	2026-09-08 22:35:14 +10:00
riley	9794f26137	Fixed error in logic unit testbench where it didn't instansiate the DUT at all as well as some faulty test cases and reset logic	2026-09-08 22:00:07 +10:00
riley	fabfba7bdd	Removed debug statement from instruction classifier testbench	2026-09-08 21:44:36 +10:00
riley	f5a2455849	Added testbench for instruction classifier and fixed compilation errors. Should be fine to synthesise but icarus does not like the constant bit extraction in the always_comb block for some reason.	2026-09-08 21:31:18 +10:00
TroubleElectrical	60e5dae43b	Added ModelSim folder (and have to add files into it as to allow for different testbench code)	2026-09-08 16:32:01 +10:00
riley	b926d71523	Updated seven segment test bench to reflect prior commit	2026-09-03 16:58:11 +10:00
riley	dd5d044da3	Fixed bit ordering in seven segment truth table and test bench	2026-09-03 16:49:46 +10:00
riley	a89a66d34d	Fixed bug where includes still refered to verilog rather than systemverilog. Inverted test cases in seven segment test bench to reflect changes made to module. There is still a bug with the module where it outputs garbage	2026-09-03 16:32:56 +10:00
riley	6668969b03	Made it clear that we are using SystemVerilog by renaming HDL files to end in .sv rather than .v	2026-09-03 16:05:52 +10:00
riley	0c21734447	Created general project structure. Only seven segment, logic unit and adder/subtractor modules and tests implemented	2026-09-03 15:25:07 +10:00