TroubleElectrical/FPGA_Uni
1
0 Fork 0
Code Issues 1 Pull Requests Actions Packages Projects Releases Wiki Activity
19 Commits 2 Branches 0 Tags
42f4e661dca3610c9a9783e35e53a39558895502
Commit Graph
19 Commits
This Branch
This Branch
All Branches
Author SHA1 Message Date
riley 42f4e661dc Implemented shifter and its test bench code fully 2026-09-08 22:35:14 +10:00
riley 9794f26137 Fixed error in logic unit testbench where it didn't instansiate the DUT at all as well as some faulty test cases and reset logic 2026-09-08 22:00:07 +10:00
riley fabfba7bdd Removed debug statement from instruction classifier testbench 2026-09-08 21:44:36 +10:00
riley f5a2455849 Added testbench for instruction classifier and fixed compilation errors. Should be fine to synthesise but icarus does not like the constant bit extraction in the always_comb block for some reason. 2026-09-08 21:31:18 +10:00
riley 00d9e3de88 Fixed error where assignment was not within a combinational/sequential block 2026-09-08 18:23:27 +10:00
TroubleElectrical 60e5dae43b Added ModelSim folder (and have to add files into it as to allow for different testbench code) 2026-09-08 16:32:01 +10:00
TroubleElectrical 2208eb4f16 Updated Q2 project and LU code such that it operates properly on the board. Changed to utilising a case statement for easier readability and also compiled and tested the code on the board. 2026-09-08 15:36:51 +10:00
TroubleElectrical 32eea036a8 Added projects for A1 q2 to q6 2026-09-04 13:12:33 +10:00
TroubleElectrical 3114cd6b80 Added the updated A1_Q1 Quartus compilation 2026-09-03 19:22:52 +10:00
riley b926d71523 Updated seven segment test bench to reflect prior commit 2026-09-03 16:58:11 +10:00
riley 3e8aa911ce Made RSIOut the LSB to correspond with wiring configuration 2026-09-03 16:56:11 +10:00
riley dd5d044da3 Fixed bit ordering in seven segment truth table and test bench 2026-09-03 16:49:46 +10:00
TroubleElectrical 31a4496904 Including quartus prime lite edition project folders for flashing the project to the board 2026-09-03 16:34:31 +10:00
riley a89a66d34d Fixed bug where includes still refered to verilog rather than systemverilog. Inverted test cases in seven segment test bench to reflect changes made to module. There is still a bug with the module where it outputs garbage 2026-09-03 16:32:56 +10:00
riley f881a4126b Inverted seven segment decoder to reflect the common anode 2026-09-03 16:27:01 +10:00
riley 6668969b03 Made it clear that we are using SystemVerilog by renaming HDL files to end in .sv rather than .v 2026-09-03 16:05:52 +10:00
riley 0c21734447 Created general project structure. Only seven segment, logic unit and adder/subtractor modules and tests implemented 2026-09-03 15:25:07 +10:00
TroubleElectrical 41252763d4 Test commit 2026-09-03 15:12:25 +10:00
TroubleElectrical 28bfe10398 Initial commit 2026-09-03 15:04:27 +10:00