 TroubleElectrical
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353923eadf
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Updated Assignment to remove ../../ includes (unnesccesary, also SYNTHESIS macro is not used by quartus, so I manually have QUARTUS_SYNTH for those includes)
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2026-10-13 15:12:00 +11:00 |
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TroubleElectrical
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19b07b649d
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Repaired last few errors in modules and ensured compilation with QUARTUS_BUILD global flag in Quartus build settings and compiled fully (no errors other than pin assignments)
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2026-10-13 13:24:44 +11:00 |
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TroubleElectrical
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e57e8f362a
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Updated assignment 2 dependency modules (currently 8 errors in compile)
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2026-10-13 12:23:52 +11:00 |
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TroubleElectrical
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8675f5b8ee
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Made Assignment 2 Quartus Project
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2026-10-13 12:04:49 +11:00 |
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TroubleElectrical
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b49e294b7d
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Updated register_file.sv with proper naming scheme and 32bit width
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2026-10-08 15:10:40 +11:00 |
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TroubleElectrical
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9e3525fcac
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Added Byte addressable ROM from Slides
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2026-10-06 16:28:23 +11:00 |
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TroubleElectrical
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3145dd6a21
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Added ROM file from MIPS Architecture Slide Part 1
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2026-10-06 16:03:03 +11:00 |
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TroubleElectrical
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179eb469c4
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Removed seven segment code from alu and asu
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2026-09-24 15:37:48 +10:00 |
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TroubleElectrical
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64cd876f12
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Added attribution for submission files
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2026-09-16 13:01:43 +10:00 |
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TroubleElectrical
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cbb5bb917a
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Added Q6 submission
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2026-09-16 12:56:48 +10:00 |
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TroubleElectrical
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ae8ac98e8d
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Added Q5 comments and sumbission
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2026-09-16 12:54:18 +10:00 |
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TroubleElectrical
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13f34e62c6
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Added Q4 sumbission and comments
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2026-09-16 12:50:58 +10:00 |
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TroubleElectrical
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7d489ab77c
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Added Q3 sumbission and integrated all includes
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2026-09-16 12:42:28 +10:00 |
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TroubleElectrical
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56ade6b426
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Added comments to Logic Unit (Q2) and added to submission file
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2026-09-16 12:38:06 +10:00 |
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TroubleElectrical
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0947f26727
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Added comments to Q1 code and made submission file
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2026-09-16 10:33:08 +10:00 |
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TroubleElectrical
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00167dabc8
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Updated ModelSim Files
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2026-09-16 10:15:08 +10:00 |
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TroubleElectrical
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afa8d9d4db
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Enabled 2 segments for seven seg display decoder (Q1), most code just needs comments
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2026-09-15 21:08:40 +10:00 |
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TroubleElectrical
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c27a04ef73
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Implemented instruction classifier on board (Q6) and added blank submission files (for now)
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2026-09-15 20:00:35 +10:00 |
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TroubleElectrical
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9583abd307
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Updated shifter (Q5) to use proper 2**width approach and corrected the logic such that C is width bits wide, and b is 2**width (as defined in Q5 B)
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2026-09-15 19:43:28 +10:00 |
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TroubleElectrical
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9d0c7011ce
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Updated ALU (Q4) with 7seg and confirmed operation on board
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2026-09-15 19:05:04 +10:00 |
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TroubleElectrical
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9e5fb6f52b
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Updated ASU (Q3) to utilise the 7seg for output, confirmed operation of Q1 to Q3 on board
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2026-09-15 16:52:48 +10:00 |
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TroubleElectrical
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05361dcf70
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Added all Testbenches to Modelsim and confirmed working operation
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2026-09-15 15:15:00 +10:00 |
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TroubleElectrical
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a73990b242
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Added ASU (Q3) testbench to the modelsim projects folder (also confirmed operation of q2)
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2026-09-10 15:24:44 +10:00 |
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TroubleElectrical
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dc32347c9b
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Updated ALU code with updated 2**width approach and assigned temporary pins to ASU (Q3)
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2026-09-09 14:27:11 +10:00 |
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TroubleElectrical
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60e5dae43b
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Added ModelSim folder (and have to add files into it as to allow for different testbench code)
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2026-09-08 16:32:01 +10:00 |
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TroubleElectrical
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2208eb4f16
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Updated Q2 project and LU code such that it operates properly on the board. Changed to utilising a case statement for easier readability and also compiled and tested the code on the board.
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2026-09-08 15:36:51 +10:00 |
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TroubleElectrical
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32eea036a8
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Added projects for A1 q2 to q6
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2026-09-04 13:12:33 +10:00 |
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TroubleElectrical
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3114cd6b80
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Added the updated A1_Q1 Quartus compilation
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2026-09-03 19:22:52 +10:00 |
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TroubleElectrical
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31a4496904
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Including quartus prime lite edition project folders for flashing the project to the board
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2026-09-03 16:34:31 +10:00 |
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TroubleElectrical
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41252763d4
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Test commit
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2026-09-03 15:12:25 +10:00 |
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